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CY8C29466, cy8c29566 cy8c29666, cy8c29866 psoc ? programmable system-on-chip? cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-12013 rev. *s revised july 7, 2011 psoc ? programmable system-on-chip features powerful harvard-architecture processor ? m8c processor speeds to 24 mhz ? two 8 8 multiply, 32-bit accumulate ? low power at high speed ? operating voltage: 3.0 v to 5.25 v ? operating voltages down to 1. 0 v using on-chip switch mode pump (smp) ? industrial temperature range: ?40 c to +85 c advanced peripherals (psoc ? blocks) ? 12 rail-to-rail analog psoc blocks provide: ? up to 14-bit analog-to-digital converters (adcs) ? up to 9-bit digital-to-analog converters (dacs) ? programmable gain amplifiers (pgas) ? programmable filters and comparators ? 16 digital psoc blocks provide: ? 8- to 32-bit timers, counters, and pulse-width modulators (pwms) ? cyclical redundancy check (crc) and pseudo random sequence (prs) modules ? up to four full-duplex universal asynchronous receiver transmitters (uarts) ? multiple serial peripheral interface (spi) masters or slaves ? can connect to all general-purpose i/o (gpio) pins ? create complex peripherals by combining blocks precision, programmable clocking ? internal 2.5% 24- / 48-mhz main oscillator ? 24- / 48-mhz with optional 32.768 khz crystal ? optional external oscillator, up to 24 mhz ? internal oscillator for watchdog and sleep flexible on-chip memory ? 32 kb flash program storage 50,000 erase/write cycles ? 2 kb static random access memory (sram) data storage ? in-system serial programming (issp) ? partial flash updates ? flexible protection modes ? electrically erasable programmable read-only memory (eeprom) emulation in flash programmable pin configurations ? 25-ma sink, 10-ma source on all gpios ? pull-up, pull-down, high z, strong, or open-drain drive modes on all gpios ? eight standard analog inputs on gpios, plus four additional analog inputs with restricted routing ? four 40 ma analog outputs on gpios ? configurable interrupt on all gpios additional system resources ? i 2 c slave, master, and multi-master to 400 khz ? watchdog and sleep timers ? user-configurable low-voltage detection (lvd) ? integrated supervisory circuit ? on-chip precision voltage reference complete development tools ? free development software (psoc designer?) ? full-featured in-circuit emulator (ice) and programmer ? full-speed emulation ? complex breakpoint structure ? 128 kb trace memory ? complex events ? c compilers, assembler, and linker digital system sram 2kb interrupt controller sleep and watchdog multiple clock sources (includes imo, ilo, pll, and eco) global digital interconnect global analog interconnect psoc core cpu core (m8c) srom flash 32kb digital block array multiply accum. switch mode pump internal voltage ref. digital clocks por and lvd system resets decimator system resources analog system analog ref. analog input muxing i 2 c system bus analog block array port 6 port 0 with analog drivers port 1 port 2 port 3 port 4 port 5 port 7 logic block diagram [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 2 of 61 contents psoc programmable system-on-chip ........................... 1 features ............................................................................. 1 logic block diagram ........................................................ 1 psoc functional overview .............................................. 3 psoc core .................................................................. 3 digital system ............................................................. 3 analog system ............................................................ 4 additional system resources ..................................... 5 psoc device characteristics . ..................................... 5 getting started .................................................................. 6 application notes ........................................................ 6 development kits ........................................................ 6 training ....................................................................... 6 cypros consultants .................................................... 6 solutions library .......................................................... 6 technical support ....................................................... 6 development tools .......................................................... 6 psoc designer software subsyst ems .......... .............. 6 designing with psoc designer ....................................... 7 select user modules ................................................... 7 configure user modules .............................................. 7 organize and connect .............. .............. ........... ......... 7 generate, verify, and debug ....................................... 7 pinouts .............................................................................. 8 28-pin part pinout ....................................................... 8 44-pin part pinout ....................................................... 9 48-pin part pinout ..................................................... 10 100-pin part pinout ................................................... 12 100-pin part pinout (on-chip debug) ....................... 14 register reference ......................................................... 16 register conventions ................................................ 16 register mapping tables .......................................... 16 electrical specifications ................................................ 19 absolute maximum ratings ... .................................... 19 operating temperature ............................................ 20 dc electrical characteristics ..................................... 20 ac electrical characteristics ..................................... 35 packaging information ................................................... 44 packaging dimensions .............................................. 44 thermal impedances ................................................ 49 capacitance on crystal pins .............. .............. ........ 49 solder reflow specifications ..................................... 49 development tool selection .. .............. .............. ........... 50 software .................................................................... 50 development kits ...................................................... 50 evaluation tools ........................................................ 50 device programmers ............. .................................... 51 accessories (emulation and programming) .. .............. 51 ordering information ...................................................... 52 ordering code definitions ..... .................................... 52 acronyms ........................................................................ 53 acronyms used ......................................................... 53 reference documents .................................................... 53 document conventions ......... .................................... 54 units of measure ....................................................... 54 numeric conventions ............ .................................... 54 glossary .......................................................................... 54 document history page ................................................ 59 sales, solutions, and legal information ...................... 61 worldwide sales and design s upport ......... .............. 61 products .................................................................... 61 psoc solutions ......................................................... 61 [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 3 of 61 psoc functional overview the psoc family consists of many programmable system-on-chip controller devices. these devices are designed to replace multiple traditional mi crocontroller unit (mcu)-based system components with one, low-cost single-chip program- mable device. psoc devices incl ude configurable blocks of analog and digital logic, as well as programmable interconnects. this architecture allows you to create customized peripheral configurations that match the requirements of each individual application. additionally, a fast central processing unit (cpu), flash program memory, sram data memory, and configurable i/o are included in a range of convenient pinouts and packages. the psoc architecture, as illustrated in the logic block diagram on page 1 , consists of four main areas: psoc core, digital system, analog system, and system resources. configurable global busing allows all of the device resources to be combined into a complete cu stom system. the psoc cy8c29x66 family can have up to five i/o ports that connect to the global digital and analog interconnects, providing access to 8 digital blocks and 12 analog blocks. psoc core the psoc core is a powerful engine that supports a rich feature set. the core includes a cpu, me mory, clocks, and configurable gpios. the m8c cpu core is a powerful processor with speeds up to 24 mhz, providing a 4 million inst ructions per second (mips) 8-bit harvard-architecture microprocessor. the cpu uses an interrupt controller with 17 vector s, to simplify programming of real-time embedded events. program execution is timed and protected using the included sleep and watchdog timers (wdt). memory uses 16 kb of flash for program storage, 256 bytes of sram for data stor age, and up to 2 kb of eeprom emulated using the flash. program flash uses four protection levels on blocks of 64 bytes, allowing cu stomized softwa re information protection (ip). the psoc device incorporates flex ible internal clock generators, including a 24 mhz internal main oscillator (imo) accurate to 2.5% over temperature and voltage. the 24 mhz imo can also be doubled to 48 mhz for use by the digital system. a low-power 32 khz internal low speed oscillator (ilo) is provided for the sleep timer and wdt. if crystal accuracy is desired, the 32.768 khz external crystal oscillator (eco) is available for use as a real-time clock (rtc) and can optionally generate a crystal-accurate 24 mhz system clock using a pll. the clocks, together with programmable clock dividers (as a system resource), provide the flexibility to integrate almost any timing requirement into the psoc device. psoc gpios provide connection to the cpu, and digital and analog resources of the device. each pin?s drive mode may be selected from eight options, allowin g great flexibility in external interfacing. every pin also has the capability to generate a system interrupt on high level, lo w level, and c hange from last read. digital system the digital system is composed of 16 digital psoc blocks. each block is an 8-bit resource that can be used alone or combined with other blocks to form 8-, 16-, 24-, and 32-bit peripherals, which are called user modules. figure 1. digital system block diagram digital system to system bus d i g i t a l c l o c k s f r o m c o r e digital psoc block array to analog system 8 row input configuration row output configuration 8 8 8 row 1 dbb10 dbb11 dcb12 dcb13 row input configuration 4 4 row output configuration row input configuration row output configuration row 2 dbb20 dbb21 dcb22 dcb23 4 4 row 0 dbb00 dbb01 dcb02 dcb03 4 4 row input configuration row output configuration row 3 dbb30 dbb31 dcb32 dcb33 4 4 gie[7:0] gio[7:0] goe[7:0] goo[7:0] global digital interconnect port 6 port 7 port 5 port 4 port 3 port 2 port 1 port 0 [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 4 of 61 digital peripheral configurations include: pwms (8- to 32-bit) pwms with dead band (8- to 32-bit) counters (8- to 32-bit) timers (8- to 32-bit) uart 8-bit with selectable parity (up to 2) spi slave and master (up to 2) i 2 c slave and multi-master ( one available as a system resource) crc generator (8- to 32-bit) irda (up to 2) prs generators (8- to 32-bit) the digital blocks can be connected to any gpio through a series of global buses that can route any signal to any pin. the buses also allow for signal multiplexing and for performing logic operations. this configurability frees your designs from the constraints of a fixed peripheral controller. digital blocks are provided in rows of four, where the number of blocks varies by psoc device family. this allows you the optimum choice of system resources for your application. family resources are shown in the table titled ?psoc device characteristics? on page 5. analog system the analog system is composed of 12 configurable blocks, each containing an opamp circuit that allows the creation of complex analog signal flows. analog peripherals are very flexible and can be customized to support specific application requirements. some of the more common psoc analog functions (most available as user modules) are: adcs (up to 4, with 6- to 14-bit resolution; selectable as incremental, delta sigma, and sar) filters (2-, 4-, 6-, and 8-pole band pass, low pass, and notch) amplifiers (up to 4, with selectable gain to 48x) instrumentation amplifiers (up to 2, with selectable gain to 93x) comparators (up to 4, with 16 selectable thresholds) dacs (up to 4, with 6-bit to 9-bit resolution) multiplying dacs (up to 4, with 6-bit to 9-bit resolution) high current output drivers (four with 30-ma drive as a core resource) 1.3-v reference (as a system resource) dtmf dialer modulators correlators peak detectors many other topologies possible analog blocks are provided in columns of three, which includes one continuous time (ct) and two switched capacitor (sc) blocks, as shown in figure 2 . figure 2. analog system block diagram acb00 acb01 block array array input configuration aci1[1:0] aci2[1:0] acb02 acb03 asc12 asd13 asd22 asc23 asd20 aci0[1:0] aci3[1:0] p0 [ 6 ] p0 [ 4 ] p0 [ 2 ] p0 [ 0 ] p2 [ 2 ] p2 [ 0 ] p2 [ 6 ] p2 [ 4 ] refin agndin p0 [ 7 ] p0 [ 5 ] p0 [ 3 ] p0 [ 1 ] p2 [ 3 ] p2 [ 1 ] re f e r e n ce ge ne r ator s agndin ref in bandgap ref hi ref lo agnd asd11 asc21 asc10 interface to digital system m8c interface (address bus, data bus, etc.) analog reference [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 5 of 61 additional system resources system resources, some of which were previously listed, provide additional capability useful to complete system s. additional resources include a multiplier, decimator, switch mode pump, low-voltage detection, and power-on-reset (por). digital clock dividers provide three customizable clock frequencies for use in applications. the clocks can be routed to both the digital and analog systems. additional clocks can be generated using di gital psoc blocks as clock dividers. multiply accumulate (mac) provides a fast 8-bit multiplier with 32-bit accumulate, to assist in general math and digital filters. the decimator provides a custom hardware filter for digital signal processing applications including the creation of delta sigma adcs. the i 2 c module provides 100 and 400 khz communication over two wires. slave, master, and multi-master modes are all supported. lvd interrupts can signal the application of falling voltage levels, while the advanced por circuit eliminates the need for a system supervisor. an internal 1.3 v reference provides an absolute reference for the analog system, including adcs and dacs. an integrated switch-mode pump (smp) generates normal operating voltages from a single 1.2 v battery cell, providing a low cost boost converter. psoc device characteristics depending on your psoc device characteri stics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. the following table lists th e resources available for specific psoc devic e groups.the psoc devi ce covered by thi s datasheet is highlighted. table 1. psoc device characteristics psoc part number digital i/o digital rows digital blocks analog inputs analog outputs analog columns analog blocks sram size flash size cy8c29x66 up to 64 4 16 up to 12 4 4 12 2 k 32 k cy8c28xxx up to 44 up to 3 up to 12 up to 44 up to 4 up to 6 up to 12 + 4 [1] 1 k 16 k cy8c27x43 up to 44 2 8 up to 12 4 4 12 256 16 k cy8c24x94 up to 56 1 4 up to 48 2 2 6 1 k 16 k cy8c24x23a up to 24 1 4 up to 12 2 2 6 256 4 k cy8c23x33 up to 26 1 4 up to 12 2 2 4 256 8 k cy8c22x45 up to 38 2 8 up to 38 0 4 6 [1] 1 k 16 k cy8c21x45 up to 24 1 4 up to 24 0 4 6 [1] 512 8 k cy8c21x34 up to 28 1 4 up to 28 0 2 4 [1] 512 8 k cy8c21x23 up to 16 1 4 up to 8 0 2 4 [1] 256 4 k cy8c20x34 up to 28 0 0 up to 28 0 0 3 [1,2] 512 8 k cy8c20xx6 up to 36 0 0 up to 36 0 0 3 [1,2] up to 2 k up to 32 k notes 1. limited analog functionality. 2. two analog blocks and one capsense ? . [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 6 of 61 getting started for in depth information, along with detailed programming details, see the psoc ? technical reference manual . for up-to-date ordering, packaging, and electrical specification information, see the latest psoc device datasheets on the web. application notes cypress application notes are an excellent introduction to the wide variety of possi ble psoc designs. development kits psoc development kits are available online from and through a growing number of regional and global distributors, which include arrow, avnet, digi-key, farnell, future electronics, and newark. training free psoc technical training (on demand, webinars, and workshops), which is available online via www.cypress.com , covers a wide variety of topics and skill levels to assist you in your designs. cypros consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant go to the cypros consultants web site. solutions library visit our growing library of solution focused designs . here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. technical support technical support ? including a searchable knowledge base articles and technical forums ? is also available online. if you cannot find an answer to your question, call our technical support hotline at 1-800-541-4736. development tools psoc designer? is the revolutionary integrated design environment (ide) that you can us e to customize psoc to meet your specific application require ments. psoc designer software accelerates system design and ti me to market. develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. then, customize your design by leveraging the dynamically generated application programming interface (api) libraries of code. finally, debug and test your designs with the integrated debug environment, incl uding in-circuit emulation and standard software debug features. psoc designer includes: application editor graphical user interface (gui) for device and user module configuration and dynamic reconfiguration extensive user module catalog integrated source-code editor (c and assembly) free c compiler with no size restrictions or time limits built-in debugger in-circuit emulation built-in support for communication interfaces: ? hardware and software i 2 c slaves and masters ? full-speed usb 2.0 ? up to four full-duplex universal asynchronous receiver/trans- mitters (uarts), spi master and slave, and wireless psoc designer supports the entire library of psoc 1 devices and runs on windows xp, windows vista, and windows 7. psoc designer software subsystems design entry in the chip-level view, choose a ba se device to work with. then select different onboard analog and digital components that use the psoc blocks, which are called user modules. examples of user modules are analog-to-digital converters (adcs), digital-to-analog converters (d acs), amplifiers, and filters. configure the user modules for your chosen application and connect them to each other and to the proper pins. then generate your project. this prepopulates your project with apis and libraries that you can us e to program your application. the tool also supports easy development of multiple configura- tions and dynamic reconfiguration. dynamic reconfiguration makes it possible to change configurations at run time. in essence, this allows you to use more than 100 percent of psoc's resources for an application. code generation tools the code generation tools work seamlessly within the psoc designer interface and have been tested with a full range of debugging tools. you can develop your design in c, assembly, or a combination of the two. assemblers . the assemblers allow you to merge assembly code seamlessly with c code. link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. c language compilers . c language compilers are available that support the psoc family of devices. the products allow you to create complete c programs for the psoc family devices. the optimizing c compilers provide all of the features of c, tailored to the psoc architecture. they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 7 of 61 debugger psoc designer has a debug environment that provides hardware in-circuit emulation, al lowing you to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow you to read and program and read and write data memory, and read and write i/o registers. you can read and write cpu registers, set and clear breakpoints, and provide program run, halt, and step control. the debugger also allows you to create a trace buffer of registers and memory locations of interest. online help system the online help system displays onl ine, context-sensitive help. designed for procedural and quick reference, each functional subsystem has its own context-se nsitive help. this system also provides tutorials and links to faqs and an online support forum to aid the designer. in-circuit emulator a low-cost, high-functionality in-circuit emulator (ice) is available for development support. this hardware can program single devices. the emulator consists of a base unit that connects to the pc using a usb port. the base unit is universal and operates with all psoc devices. emulation pods for each device family are available separately. the emulat ion pod takes the place of the psoc device in the target board and performs full-speed (24 mhz) operation. designing with psoc designer the development process for the psoc? device differs from that of a traditional fixed function mi croprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divi dends in managing specification change during development and by lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variet y of user-selectable functions. the psoc development process is summarized in four steps: 1. select user modules . 2. configure user modules. 3. organize and connect. 4. generate, verify, and debug. select user modules psoc designer provides a library of prebuilt, pretested hardware peripheral components called ?user modules.? user modules make selecting and implementing peripheral devices, both analog and digital, simple. configure user modules each user module that you select establishes the basic register settings that implement the select ed function. they also provide parameters and properties that allow you to tailor their precise configuration to your particular application. for example, a pulse width modulator (pwm) user module configures one or more digital psoc blocks, one for each 8 bits of resolu tion. the user module parameters permit you to establish the pulse width and duty cycle. configure the parameters and properties to corre- spond to your chosen application. enter values directly or by selecting values from drop-dow n menus. all the user modules are documented in datasheets that may be viewed directly in psoc designer or on the cypress website. these user module datasheets explain the internal operation of the user module and provide performance specifications. each datasheet describes the use of each user module parameter, and other information you may need to successfully implement your design. organize and connect you build signal chains at the chip level by interconnecting user modules to each other and the i/o pins. you perform the selection, configuration, and routing so that you have complete control over all on-chip resources. generate, verify, and debug when you are ready to test the hardware configuration or move on to developing code for the project, you perform the ?generate configuration files? step. this causes psoc designer to generate source code that automatic ally configures the device to your specification and provides the software for the system. the generated code provides application programming interfaces (apis) with high-level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed. a complete code development environment allows you to develop and customize your applications in either c, assembly language, or both. the last step in the development process takes place inside psoc designer?s debugger (access by clicking the connect icon). psoc designer downloads the hex image to the ice where it runs at full speed. psoc designer debugging capabil- ities rival those of systems cost ing many times more. in addition to traditional single-step, run-to-breakpoint and watch-variable features, the debug interface prov ides a large trace buffer and allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 8 of 61 pinouts the cy8c29x66 psoc device is available in a variety of package s which are listed and illustrated in the following tables. every port pin (labeled with a ?p?) is capable of digital i/o. however, v ss , v dd , smp, and xres are not capable of digital i/o. 28-pin part pinout note 3. these are the issp pins, which are not high z at power on reset (por). see the psoc programmable system-on-chip technical reference manual for details. table 2. 28-pin part pinout (pdip, ssop, soic) pin no. type pin name description figure 3. CY8C29466 28-pin psoc device digital analog 1 i/o i p0[7] analog column mux input 2 i/o i/o p0[5] analog column mux input and column output 3 i/o i/o p0[3] analog column mux input and column output 4 i/o i p0[1] analog column mux input 5 i/o p2[7] 6 i/o p2[5] 7 i/o i p2[3] direct switched capacitor block input 8 i/o i p2[1] direct switched capacitor block input 9 power smp switch mode pump (smp) connection to external components required 10 i/o p1[7] i 2 c serial clock (scl) 11 i/o p1[5] i 2 c serial data (sda) 12 i/o p1[3] 13 i/o p1[1] crystal (xtalin), i 2 c serial clock (scl), issp-sclk [3] 14 power v ss ground connection 15 i/o p1[0] crystal (xtalout), i 2 c serial data (sda), issp-sdata [3] 16 i/o p1[2] 17 i/o p1[4] optional external clock input (extclk) 18 i/o p1[6] 19 input xres active high external reset with internal pull-down 20 i/o i p2[0] direct switched capacitor block input 21 i/o i p2[2] direct switched capacitor block input 22 i/o p2[4] external analog ground (agnd) 23 i/o p2[6] external voltage reference (vref) 24 i/o i p0[0] analog column mux input 25 i/o i/o p0[2] analog column mux input and column output 26 i/o i/o p0[4] analog column mux input and column output 27 i/o i p0[6] analog column mux input 28 power v dd supply voltage legend : a = analog, i = input, and o = output. a, i, p0[7] a, io, p0[5] a, io, p0[3] a, i, p0[1] p2[7] p2[5] a, i, p2[3] a, i, p2[1] smp i2c scl, p1[7] i2c sda, p1[5] p1[3] i2c scl, xtalin, p1[1] v ss v dd p0[6], a, i p0[4], a, io p0[2], a, io p0[0], a, i p2[6], external vref p2[4], external agnd p2[2], a, i p2[0], a, i xres p1[6] p1[4], extclk p1[2] p1[0], xtalout, i2csda pdip ssop soic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 9 of 61 44-pin part pinout note 4. these are the issp pins, which are not high z at por. see the psoc programmable system-on-chip technical reference manual for details. table 3. 44-pin part pinout (tqfp) pin no. type pin name description figure 4. cy8c29566 44-pin psoc device digital analog 1 i/o p2[5] 2 i/o i p2[3] direct switched capacitor block input 3 i/o i p2[1] direct switched capacitor block input 4 i/o p4[7] 5 i/o p4[5] 6 i/o p4[3] 7 i/o p4[1] 8 power smp switch mode pump (smp) connection to external components required 9 i/o p3[7] 10 i/o p3[5] 11 i/o p3[3] 12 i/o p3[1] 13 i/o p1[7] i 2 c scl 14 i/o p1[5] i 2 c sda 15 i/o p1[3] 16 i/o p1[1] crystal (xtalin), i 2 c scl, issp-sclk [4] 17 power v ss ground connection 18 i/o p1[0] crystal (xtalout), i 2 c sda, issp-sdata [4] 19 i/o p1[2] 20 i/o p1[4] optional extclk 21 i/o p1[6] 22 i/o p3[0] 23 i/o p3[2] 24 i/o p3[4] 25 i/o p3[6] 26 input xres active high external reset with internal pull-down 27 i/o p4[0] 28 i/o p4[2] 29 i/o p4[4] 30 i/o p4[6] 31 i/o i p2[0] direct switched capacitor block input 32 i/o i p2[2] direct switched capacitor block input 33 i/o p2[4] external analog ground (agnd) 34 i/o p2[6] external voltage reference (vref) 35 i/o i p0[0] analog column mux input 36 i/o i/o p0[2] analog column mux input and column output 37 i/o i/o p0[4] analog column mux input and column output 38 i/o i p0[6] analog column mux input 39 power v dd supply voltage 40 i/o i p0[7] analog column mux input 41 i/o i/o p0[5] analog column mux input and column output 42 i/o i/o p0[3] analog column mux input and column output 43 i/o i p0[1] analog column mux input 44 i/o p2[7] legend : a = analog, i = input, and o = output. tqfp p3[1] p2[7] p2[5] p2[4], external agnd a, i, p2[3] p2[2], a, i a, i, p2[1] p2[0], a, i p4[7] p4[6] p4[5] p4[4] p4[3] p4[2] p4[1] p4[0] smp xres p3[7] p3[6] p3[5] p3[4] p3[3] p3[2] i2c scl, p1[7] p0[1], a, i i2c sda, p1[5] p0[3], a, io p1[3] p0[5], a, io i2c scl, xtalin, p1[1] p0[7], a, i v ss v dd i2c sda, xtalout, p1[0] p0[6], a, i p1[2] p0[4], a, io extclk, p1[4] p0[2], a, io p1[6] p0[0], a, i p3[0] p2[6], external vref 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 13 14 15 16 17 18 19 20 21 22 12 [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 10 of 61 48-pin part pinout note 5. these are the issp pins, which are not high z at por. see the psoc programmable system-on-chip technical reference manual for details. table 4. 48-pin part pinout (ssop) pin no. type pin name description figure 5. cy8c29666 48-pin psoc device digital analog 1 i/o i p0[7] analog column mux input 2 i/o i/o p0[5] analog column mux input and column output 3 i/o i/o p0[3] analog column mux input and column output 4 i/o i p0[1] analog column mux input 5 i/o p2[7] 6 i/o p2[5] 7 i/o i p2[3] direct switched capacitor block input 8 i/o i p2[1] direct switched capacitor block input 9 i/o p4[7] 10 i/o p4[5] 11 i/o p4[3] 12 i/o p4[1] 13 power smp switch mode pump (smp) connection to external components required 14 i/o p3[7] 15 i/o p3[5] 16 i/o p3[3] 17 i/o p3[1] 18 i/o p5[3] 19 i/o p5[1] 20 i/o p1[7] i 2 c scl 21 i/o p1[5] i 2 c sda 22 i/o p1[3] 23 i/o p1[1] crystal (xtalin), i 2 c scl, issp-sclk [5] 24 power v ss ground connection 25 i/o p1[0] crystal (xtalout), i 2 c sda, issp-sdata [5] 26 i/o p1[2] 27 i/o p1[4] optional extclk 28 i/o p1[6] 29 i/o p5[0] 30 i/o p5[2] 31 i/o p3[0] 32 i/o p3[2] 33 i/o p3[4] 34 i/o p3[6] 35 input xres active high external reset with internal pull-down 36 i/o p4[0] 37 i/o p4[2] 38 i/o p4[4] 39 i/o p4[6] 40 i/o i p2[0] direct switched capacitor block input 41 i/o i p2[2] direct switched capacitor block input 42 i/o p2[4] external analog ground (agnd) 43 i/o p2[6] external voltage reference (vref) 44 i/o i p0[0] analog column mux input 45 i/o i/o p0[2] analog column mux input and column output 46 i/o i/o p0[4] analog column mux input and column output 47 i/o i p0[6] analog column mux input 48 power v dd supply voltage legend: a = analog, i = input, and o = output. ssop a, i, p0[7] v dd a, io, p0[5] p0[6], a, i a, io, p0[3] p0[2], a, io a, i, p0[1] p0[4], a, io p2[7] p0[0], a, i p2[5] p2[6], external vref a, i, p2[3] p2[4], external agnd a, i, p2[1] p2[2], a, i p4[7] p2[0], a, i p4[5] p4[6] p4[3] p4[4] p4[1] p4[2] smp p4[0] p3[7] xres p3[5] p3[6] p3[3] p3[4] p3[1] p3[2] p5[3] p3[0] p5[1] p5[2] i2c scl, p1[7] p5[0] i2c sda, p1[5] p1[6] p1[3] p1[4], extclk i2c scl, xtalin, p1[1] p1[2] v ss p1[0], xtalout, i2c sda 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 43 44 42 40 41 39 38 37 36 35 33 34 32 31 30 29 28 27 26 25 [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 11 of 61 table 5. 48-pin part pinout (qfn) [7] notes 6. these are the issp pins, which are not high z at por. see the psoc programmable system-on-chip technical reference manual for details. 7. the qfn package has a center pad that must be connected to ground (v ss ). pin no. type pin name description figure 6. cy8c29666 48-pin psoc device digital analog 1 i/o i p2[3] direct switched capacitor block input 2 i/o i p2[1] direct switched capacitor block input 3 i/o p4[7] 4 i/o p4[5] 5 i/o p4[3] 6 i/o p4[1] 7 power smp switch mode pump (smp) connection to external components required 8 i/o p3[7] 9 i/o p3[5] 10 i/o p3[3] 11 i/o p3[1] 12 i/o p5[3] 13 i/o p5[1] 14 i/o p1[7] i 2 c scl 15 i/o p1[5] i 2 c sda 16 i/o p1[3] 17 i/o p1[1] crystal (xtalin), i 2 c scl, issp-sclk [6] 18 power v ss ground connection 19 i/o p1[0] crystal (xtalout), i 2 c sda, issp-sdata [6] 20 i/o p1[2] 21 i/o p1[4] optional extclk 22 i/o p1[6] 23 i/o p5[0] 24 i/o p5[2] 25 i/o p3[0] 26 i/o p3[2] 27 i/o p3[4] 28 i/o p3[6] 29 input xres active high external reset with internal pull-down 30 i/o p4[0] 31 i/o p4[2] 32 i/o p4[4] 33 i/o p4[6] 34 i/o i p2[0] direct switched capacitor block input 35 i/o i p2[2] direct switched capacitor block input 36 i/o p2[4] external analog ground (agnd) 37 i/o p2[6] external voltage reference (vref) 38 i/o i p0[0] analog column mux input 39 i/o i/o p0[2] analog column mux input and column output 40 i/o i/o p0[4] analog column mux input and column output 41 i/o i p0[6] analog column mux input 42 power v dd supply voltage 43 i/o i p0[7] analog column mux input 44 i/o i/o p0[5] analog column mux input and column output 45 i/o i/o p0[3] analog column mux input and column output 46 i/o i p0[1] analog column mux input 47 i/o p2[7] 48 i/o p2[5] legend : a = analog, i = input, and o = output. qfn (top view) p2[5] p2[7] p0[1], a, i p0[3], a, io p0[5], a, io p0[7], a, i v dd p0[6], a, i p0[4], a, io p0[2], a, io p0[0], a, i p2[6], external vref 10 11 12 a, i, p2[3] a, i, p2[1] p4[7] p4[5] p4[3] p4[1] smp p3[7] p3[5] p3[3] p3[1] p5[3] 35 34 33 32 31 30 29 28 27 26 25 36 48 47 46 45 44 43 42 41 40 39 38 37 p2[2], a, i p2[0], a, i p4[6] p4[4] p4[2] p4[0] xres p3[6] p3[4] p3[2] p3[0] p2[4], external agnd 1 2 3 4 5 6 7 8 9 13 14 15 16 17 18 19 20 21 22 23 24 p5[1] i2c scl, p1[7] i2c sda, p1[5] p1[3] i2c scl, xtalin, p1[1] v ss i2c sda, xtalout, p1[0] p1[2] extclk, p1[4] p1[6] p5[0] p5[2] [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 12 of 61 100-pin part pinout note 8. these are the issp pins, which are not high z at por. see the psoc programmable system-on-chip technical reference manual for details. table 6. 100-pin part pinout (tqfp) pin no. type name description pin no. type name description digital analog digital analog 1 nc no connection 51 nc no connection 2 nc no connection 52 i/o p5[0] 3 i/o i p0[1] analog column mux input 53 i/o p5[2] 4 i/o p2[7] 54 i/o p5[4] 5 i/o p2[5] 55 i/o p5[6] 6 i/o i p2[3] direct switched capacitor block input 56 i/o p3[0] 7 i/o i p2[1] direct switched capacitor block input 57 i/o p3[2] 8 i/o p4[7] 58 i/o p3[4] 9 i/o p4[5] 59 i/o p3[6] 10 i/o p4[3] 60 nc no connection 11 i/o p4[1] 61 nc no connection 12 nc no connection 62 input xres active high external reset with internal pull-down 13 nc no connection 63 i/o p4[0] 14 power smp switch mode pump (smp) connection to external components required 64 i/o p4[2] 15 power v ss ground connection 65 power v ss ground connection 16 i/o p3[7] 66 i/o p4[4] 17 i/o p3[5] 67 i/o p4[6] 18 i/o p3[3] 68 i/o i p2[0] direct switched capacitor block input 19 i/o p3[1] 69 i/o i p2[2] direct switched capacitor block input 20 i/o p5[7] 70 i/o p2[4] external analog ground (agnd) 21 i/o p5[5] 71 nc no connection 22 i/o p5[3] 72 i/o p2[6] external voltage reference (vref) 23 i/o p5[1] 73 nc no connection 24 i/o p1[7] i 2 c scl 74 i/o i p0[0] analog column mux input 25 nc no connection 75 nc no connection 26 nc no connection 76 nc no connection 27 nc no connection 77 i/o i/o p0[2] analog column mux input and column output 28 i/o p1[5] i 2 c sda 78 nc no connection 29 i/o p1[3] 79 i/o i/o p0[4] analog column mux input and column output 30 i/o p1[1] crystal (xtalin), i 2 c serial clock (scl), issp-sclk [8] 80 nc no connection 31 nc no connection 81 i/o i p0[6] analog column mux input 32 power v dd supply voltage 82 power v dd supply voltage 33 nc no connection 83 power v dd supply voltage 34 power v ss ground connection 84 power v ss ground connection 35 nc no connection 85 power v ss ground connection 36 i/o p7[7] 86 i/o p6[0] 37 i/o p7[6] 87 i/o p6[1] 38 i/o p7[5] 88 i/o p6[2] 39 i/o p7[4] 89 i/o p6[3] 40 i/o p7[3] 90 i/o p6[4] 41 i/o p7[2] 91 i/o p6[5] 42 i/o p7[1] 92 i/o p6[6] 43 i/o p7[0] 93 i/o p6[7] 44 i/o p1[0] crystal (xtalout), i 2 c serial data (sda), issp-sdata [8] 94 nc no connection 45 i/o p1[2] 95 i/o i p0[7] analog column mux input 46 i/o p1[4] optional extclk 96 nc no connection 47 i/o p1[6] 97 i/o i/o p0[5] analog column mux input and column output 48 nc no connection 98 nc no connection 49 nc no connection 99 i/o i/o p0[3] analog column mux input and column output 50 nc no connection 100 nc no connection legend : a = analog, i = input, and o = output. [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 13 of 61 figure 7. cy8c29866 100-pin psoc device tqfp nc nc a, i, p0[1] p2[7] p2[5] a, i, p2[3] a, i, p2[1] p4[7] p4[5] p4[3] p4[1] nc nc smp v ss p3[7] p3[5] p3[3] p3[1] p5[7] p5[5] p5[3] p5[1] i2c scl, p1[7] nc nc v ss p7[3] extclk, p1[4] nc i2c sda, p1[5] p1[3] xtalin, i2c scl, p1[1] nc v dd nc nc p7[7] p7[6] p7[5] p7[4] p7[2] p7[1] p7[0] xtalout, i2c sda, p1[0] p1[2] p1[6] nc nc nc nc p0[0], a, i nc p2[6], external vref nc p2[4], external agnd p2[2], a, i p2[0], a, i p4[6] p4[4] v ss p4[2] p4[0] xres nc nc p3[6] p3[4] p3[2] p3[0] p5[6] p5[4] p5[2] p5[0] nc nc p0[3], a, io nc p0[5], a, io nc p0[7], a, i nc p6[7] p6[6] p6[5] p6[4] p6[3] p6[2] p6[1] p6[0] v ss v ss v dd v dd p0[6], a, i nc p0[4], a, io nc p0[2], a, io nc 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 50 49 [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 14 of 61 100-pin part pinout (on-chip debug) the 100-pin tqfp part is for the cy8c29000 on-chip debug (ocd) psoc device. note ocd parts are only used for in-circuit debuggi ng. ocd parts are not available for production table 7. 100-pin ocd part pinout (tqfp) pin no. digital analog name description pin no. digital analog name description 1 nc no internal connection 51 nc no internal connection 2 nc no internal connection 52 i/o p5[0] 3 i/o i p0[1] analog column mux input 53 i/o p5[2] 4 i/o p2[7] 54 i/o p5[4] 5 i/o p2[5] 55 i/o p5[6] 6 i/o i p2[3] direct switched capacitor block input 56 i/o p3[0] 7 i/o i p2[1] direct switched capacitor block input 57 i/o p3[2] 8 i/o p4[7] 58 i/o p3[4] 9 i/o p4[5] 59 i/o p3[6] 10 i/o p4[3] 60 hclk ocd high speed clock output 11 i/o p4[1] 61 cclk ocd cpu clock output 12 ocde ocd even data i/o 62 input xres active high pin reset with internal pull-down 13 ocdo ocd odd data output 63 i/o p4[0] 14 power smp switch mode pump (smp) connection to required external components 64 i/o p4[2] 15 power v ss ground connection 65 power v ss ground connection 16 i/o p3[7] 66 i/o p4[4] 17 i/o p3[5] 67 i/o p4[6] 18 i/o p3[3] 68 i/o i p2[0] direct switched capacitor block input 19 i/o p3[1] 69 i/o i p2[2] direct switched capacitor block input 20 i/o p5[7] 70 i/o p2[4] external analog ground (agnd) input 21 i/o p5[5] 71 nc no internal connection 22 i/o p5[3] 72 i/o p2[6] external voltage reference (vref) input 23 i/o p5[1] 73 nc no internal connection 24 i/o p1[7] i 2 c scl 74 i/o i p0[0] analog column mux input 25 nc no internal connection 75 nc no internal connection 26 nc no internal connection 76 nc no internal connection 27 nc no internal connection 77 i/o i/o p0[2] analog column mux input and column output 28 i/o p1[5] i 2 c sda 78 nc no internal connection 29 i/o p1[3] i fmtest 79 i/o i/o p0[4] analog column mux input and column output, v ref 30 i/o p1[1] [9] crystal (xtalin), i 2 c scl, tc sclk. 80 nc no internal connection 31 nc no internal connection 81 i/o i p0[6] analog column mux input 32 power v dd supply voltage 82 power v dd supply voltage 33 nc no internal connection 83 power v dd supply voltage 34 power v ss ground connection 84 power v ss ground connection 35 nc no internal connection 85 power v ss ground connection 36 i/o p7[7] 86 i/o p6[0] 37 i/o p7[6] 87 i/o p6[1] 38 i/o p7[5] 88 i/o p6[2] 39 i/o p7[4] 89 i/o p6[3] 40 i/o p7[3] 90 i/o p6[4] 41 i/o p7[2] 91 i/o p6[5] 42 i/o p7[1] 92 i/o p6[6] 43 i/o p7[0] 93 i/o p6[7] 44 i/o p1[0]* crystal (xtalout), i 2 c sda, tc sdata 94 nc no internal connection 45 i/o p1[2] v fmtest 95 i/o i p0[7] analog column mux input 46 i/o p1[4] optional external clock input (extclk) 96 nc no internal connection 47 i/o p1[6] 97 i/o i/o p0[5] analog column mux input and column output 48 nc no internal connection 98 nc no internal connection 49 nc no internal connection 99 i/o i/o p0[3] analog column mux input and column output 50 nc no internal connection 100 nc no internal connection legend a = analog, i = input, o = output, nc = no connection, tc/tm: test. note 9. issp pin which is not high-z at por. [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 15 of 61 figure 8. cy8c29000 ocd (not for production) ocd tqfp 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 nc nc ai , p0[1] p2[7] p2[5] ai , p2[3] ai , p2[1] p4[7] p4[5] p4[3] p4[1] ocde ocdo smp vss p3[7] p3[5] p3[3] p3[1] p5[7] p5[5] p5[3] p5[1] i2 c scl, p1[7] nc 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 50 49 nc v ss p7[3] extclk, p1[4] nc i2c sda, p1[5] p1[3] xtalin, i2c scl, p1[1] nc nc nc p7[7] p7[6] p7[5] p7[4] p7[2] p7[1] p7[0] xtalout, i2c sda, p1[0] p1[2] p1[6] nc nc nc 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 nc p0[0] , ai nc p2[6] , external vref nc p2[4] , external agnd p2[2] , ai p2[0] , ai p4[6] p4[4] v ss p4[2] p4[0] xres cclk hclk p3[6] p3[4] p3[2] p3[0] p5[6] p5[4] p5[2] p5[0] nc nc p0[3], aio nc p0[5], aio nc p0[7], ai nc p6[7] p6[6] p6[5] p6[4] p6[3] p6[2] p6[1] p6[0] v ss v ss v dd v dd p0[6], ai nc p0[4], aio nc p0[2], aio nc v dd [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 16 of 61 register reference this section lists the registers of the cy8c29x66 psoc device. for detailed register information, refer to the psoc programmable system-on-chip technical reference manual . register conventions the register conventions specific to this section are listed in ta b l e 8 . register mapping tables the psoc device has a total register address space of 512 bytes. the register space is referred to as i/o space and is divided into two banks. the xoi bit in the flag register (cpu_f) determines wh ich bank the user is currently in. when the xoi bit is set the user is in bank 1. note in the register mapping tables, blank fi elds are reserved and should not be accessed. table 8. register conventions convention description r read register or bit(s) w write register or bit(s) l logical register or bit(s) c clearable register or bit(s) # access is bit specific [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 17 of 61 table 9. register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw dbb20dr0 40 # asc10cr0 80 rw rdi2ri c0 rw prt0ie 01 rw dbb20dr1 41 w asc10cr1 81 rw rdi2syn c1 rw prt0gs 02 rw dbb20dr2 42 rw asc10cr2 82 rw rdi2is c2 rw prt0dm2 03 rw dbb20cr0 43 # asc10cr3 83 rw rdi2lt0 c3 rw prt1dr 04 rw dbb21dr0 44 # asd11cr0 84 rw rdi2lt1 c4 rw prt1ie 05 rw dbb21dr1 45 w asd11cr1 85 rw rdi2ro0 c5 rw prt1gs 06 rw dbb21dr2 46 rw asd11cr2 86 rw rdi2ro1 c6 rw prt1dm2 07 rw dbb21cr0 47 # asd11cr3 87 rw c7 prt2dr 08 rw dcb22dr0 48 # asc12cr0 88 rw rdi3ri c8 rw prt2ie 09 rw dcb22dr1 49 w asc12cr1 89 rw rdi3syn c9 rw prt2gs 0a rw dcb22dr2 4a rw asc12cr2 8a rw rdi3is ca rw prt2dm2 0b rw dcb22cr0 4b # asc12cr3 8b rw rdi3lt0 cb rw prt3dr 0c rw dcb23dr0 4c # asd13cr0 8c rw rdi3lt1 cc rw prt3ie 0d rw dcb23dr1 4d w asd13cr1 8d rw rdi3ro0 cd rw prt3gs 0e rw dcb23dr2 4e rw asd13cr2 8e rw rdi3ro1 ce rw prt3dm2 0f rw dcb23cr0 4f # asd13cr3 8f rw cf prt4dr 10 rw dbb30dr0 50 # asd20cr0 90 rw cur_pp d0 rw prt4ie 11 rw dbb30dr1 51 w asd20cr1 91 rw stk_pp d1 rw prt4gs 12 rw dbb30dr2 52 rw asd20cr2 92 rw d2 prt4dm2 13 rw dbb30cr0 53 # asd20cr3 93 rw idx_pp d3 rw prt5dr 14 rw dbb31dr0 54 # asc21cr0 94 rw mvr_pp d4 rw prt5ie 15 rw dbb31dr1 55 w asc21cr1 95 rw mvw_pp d5 rw prt5gs 16 rw dbb31dr2 56 rw asc21cr2 96 rw i2c_cfg d6 rw prt5dm2 17 rw dbb31cr0 57 # asc21cr3 97 rw i2c_scr d7 # prt6dr 18 rw dcb32dr0 58 # asd22cr0 98 rw i2c_dr d8 rw prt6ie 19 rw dcb32dr1 59 w asd22cr1 99 rw i2c_mscr d9 # prt6gs 1a rw dcb32dr2 5a rw asd22cr2 9a rw int_clr0 da rw prt6dm2 1b rw dcb32cr0 5b # asd22cr3 9b rw int_clr1 db rw prt7dr 1c rw dcb33dr0 5c # asc23cr0 9c rw int_clr2 dc rw prt7ie 1d rw dcb33dr1 5d w asc23cr1 9d rw int_clr3 dd rw prt7gs 1e rw dcb33dr2 5e rw asc23cr2 9e rw int_msk3 de rw prt7dm2 1f rw dcb33cr0 5f # asc23cr3 9f rw int_msk2 df rw dbb00dr0 20 # amx_in 60 rw a0 int_msk0 e0 rw dbb00dr1 21 w 61 a1 int_msk1 e1 rw dbb00dr2 22 rw 62 a2 int_vc e2 rc dbb00cr0 23 # arf_cr 63 rw a3 res_wdt e3 w dbb01dr0 24 # cmp_cr0 64 # a4 dec_dh e4 rc dbb01dr1 25 w asy_cr 65 # a5 dec_dl e5 rc dbb01dr2 26 rw cmp_cr1 66 rw a6 dec_cr0 e6 rw dbb01cr0 27 # 67 a7 dec_cr1 e7 rw dcb02dr0 28 # 68 mul1_x a8 w mul0_x e8 w dcb02dr1 29 w 69 mul1_y a9 w mul0_y e9 w dcb02dr2 2a rw 6a mul1_dh aa r mul0_dh ea r dcb02cr0 2b # 6b mul1_dl ab r mul0_dl eb r dcb03dr0 2c # tmp_dr0 6c rw acc1_dr1 ac rw acc0_dr1 ec rw dcb03dr1 2d w tmp_dr1 6d rw acc1_dr0 ad rw acc0_dr0 ed rw dcb03dr2 2e rw tmp_dr2 6e rw acc1_dr3 ae rw acc0_dr3 ee rw dcb03cr0 2f # tmp_dr3 6f rw acc1_dr2 af rw acc0_dr2 ef rw dbb10dr0 30 # acb00cr3 70 rw rdi0ri b0 rw f0 dbb10dr1 31 w acb00cr0 71 rw rdi0syn b1 rw f1 dbb10dr2 32 rw acb00cr1 72 rw rdi0is b2 rw f2 dbb10cr0 33 # acb00cr2 73 rw rdi0lt0 b3 rw f3 dbb11dr0 34 # acb01cr3 74 rw rdi0lt1 b4 rw f4 dbb11dr1 35 w acb01cr0 75 rw rdi0ro0 b5 rw f5 dbb11dr2 36 rw acb01cr1 76 rw rdi0ro1 b6 rw f6 dbb11cr0 37 # acb01cr2 77 rw b7 cpu_f f7 rl dcb12dr0 38 # acb02cr3 78 rw rdi1ri b8 rw f8 dcb12dr1 39 w acb02cr0 79 rw rdi1syn b9 rw f9 dcb12dr2 3a rw acb02cr1 7a rw rdi1is ba rw fa dcb12cr0 3b # acb02cr2 7b rw rdi1lt0 bb rw fb dcb13dr0 3c # acb03cr3 7c rw rdi1lt1 bc rw fc dcb13dr1 3d w acb03cr0 7d rw rdi1ro0 bd rw fd dcb13dr2 3e rw acb03cr1 7e rw rdi1ro1 be rw cpu_scr1 fe # dcb13cr0 3f # acb03cr2 7f rw bf cpu_scr0 ff # blank fields are reserved and should not be accessed. # acce ss is bit specific. [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 18 of 61 table 10. register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw dbb20fn 40 rw asc10cr0 80 rw rdi2ri c0 rw prt0dm1 01 rw dbb20in 41 rw asc10cr1 81 rw rdi2syn c1 rw prt0ic0 02 rw dbb20ou 42 rw asc10cr2 82 rw rdi2is c2 rw prt0ic1 03 rw 43 asc10cr3 83 rw rdi2lt0 c3 rw prt1dm0 04 rw dbb21fn 44 rw asd11cr0 84 rw rdi2lt1 c4 rw prt1dm1 05 rw dbb21in 45 rw asd11cr1 85 rw rdi2ro0 c5 rw prt1ic0 06 rw dbb21ou 46 rw asd11cr2 86 rw rdi2ro1 c6 rw prt1ic1 07 rw 47 asd11cr3 87 rw c7 prt2dm0 08 rw dcb22fn 48 rw asc12cr0 88 rw rdi3ri c8 rw prt2dm1 09 rw dcb22in 49 rw asc12cr1 89 rw rdi3syn c9 rw prt2ic0 0a rw dcb22ou 4a rw asc12cr2 8a rw rdi3is ca rw prt2ic1 0b rw 4b asc12cr3 8b rw rdi3lt0 cb rw prt3dm0 0c rw dcb23fn 4c rw asd13cr0 8c rw rdi3lt1 cc rw prt3dm1 0d rw dcb23in 4d rw asd13cr1 8d rw rdi3ro0 cd rw prt3ic0 0e rw dcb23ou 4e rw asd13cr2 8e rw rdi3ro1 ce rw prt3ic1 0f rw 4f asd13cr3 8f rw cf prt4dm0 10 rw dbb30fn 50 rw asd20cr0 90 rw gdi_o_in d0 rw prt4dm1 11 rw dbb30in 51 rw asd20cr1 91 rw gdi_e_in d1 rw prt4ic0 12 rw dbb30ou 52 rw asd20cr2 92 rw gdi_o_ou d2 rw prt4ic1 13 rw 53 asd20cr3 93 rw gdi_e_ou d3 rw prt5dm0 14 rw dbb31fn 54 rw asc21cr0 94 rw d4 prt5dm1 15 rw dbb31in 55 rw asc21cr1 95 rw d5 prt5ic0 16 rw dbb31ou 56 rw asc21cr2 96 rw d6 prt5ic1 17 rw 57 asc21cr3 97 rw d7 prt6dm0 18 rw dcb32fn 58 rw asd22cr0 98 rw d8 prt6dm1 19 rw dcb32in 59 rw asd22cr1 99 rw d9 prt6ic0 1a rw dcb32ou 5a rw asd22cr2 9a rw da prt6ic1 1b rw 5b asd22cr3 9b rw db prt7dm0 1c rw dcb33fn 5c rw asc23cr0 9c rw dc prt7dm1 1d rw dcb33in 5d rw asc23cr1 9d rw osc_go_en dd rw prt7ic0 1e rw dcb33ou 5e rw asc23cr2 9e rw osc_cr4 de rw prt7ic1 1f rw 5f asc23cr3 9f rw osc_cr3 df rw dbb00fn 20 rw clk_cr0 60 rw a0 osc_cr0 e0 rw dbb00in 21 rw clk_cr1 61 rw a1 osc_cr1 e1 rw dbb00ou 22 rw abf_cr0 62 rw a2 osc_cr2 e2 rw 23 amd_cr0 63 rw a3 vlt_cr e3 rw dbb01fn 24 rw 64 a4 vlt_cmp e4 r dbb01in 25 rw 65 a5 e5 dbb01ou 26 rw amd_cr1 66 rw a6 e6 27 alt_cr0 67 rw a7 dec_cr2 e7 rw dcb02fn 28 rw alt_cr1 68 rw a8 imo_tr e8 w dcb02in 29 rw clk_cr2 69 rw a9 ilo_tr e9 w dcb02ou 2a rw 6a aa bdg_tr ea rw 2b 6b ab eco_tr eb w dcb03fn 2c rw tmp_dr0 6c rw ac ec dcb03in 2d rw tmp_dr1 6d rw ad ed dcb03ou 2e rw tmp_dr2 6e rw ae ee 2f tmp_dr3 6f rw af ef dbb10fn 30 rw acb00cr3 70 rw rdi0ri b0 rw f0 dbb10in 31 rw acb00cr0 71 rw rdi0syn b1 rw f1 dbb10ou 32 rw acb00cr1 72 rw rdi0is b2 rw f2 33 acb00cr2 73 rw rdi0lt0 b3 rw f3 dbb11fn 34 rw acb01cr3 74 rw rdi0lt1 b4 rw f4 dbb11in 35 rw acb01cr0 75 rw rdi0ro0 b5 rw f5 dbb11ou 36 rw acb01cr1 76 rw rdi0ro1 b6 rw f6 37 acb01cr2 77 rw b7 cpu_f f7 rl dcb12fn 38 rw acb02cr3 78 rw rdi1ri b8 rw f8 dcb12in 39 rw acb02cr0 79 rw rdi1syn b9 rw f9 dcb12ou 3a rw acb02cr1 7a rw rdi1is ba rw fls_pr1 fa rw 3b acb02cr2 7b rw rdi1lt0 bb rw fb dcb13fn 3c rw acb03cr3 7c rw rdi1lt1 bc rw fc dcb13in 3d rw acb03cr0 7d rw rdi1ro0 bd rw fd dcb13ou 3e rw acb03cr1 7e rw rdi1ro1 be rw cpu_scr1 fe # 3f acb03cr2 7f rw bf cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 19 of 61 electrical specifications this section presents the dc and ac electr ical specifications of the cy8c29x66 psoc device. for the most up-to-date electrical specifications, confirm that you have the most recent datasheet by going to the web at http://www.cypress.com. specifications are valid for ?40 c t a 85 c and t j 100 c, except where noted. refer to table 27 for the electrical specifications on the internal main oscillator (imo) using slimo mode. figure 9. voltage versus cpu frequency figure 10. imo frequency options absolute maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. 5.25 4.75 3.00 93 khz 12 mhz 24 mhz cpu frequency vdd voltage 5.25 4.75 3.00 93 khz 12 mhz 24 mhz im o frequency vdd voltage 3.60 6 mhz slimo mode = 0 slimo mode=0 slimo mode=1 v a l i d o p e r a t i n g r eg i o n slimo mode=1 slimo mode=0 table 11. absolute maximum ratings symbol description min typ max unit notes t stg storage temperature ?55 25 +100 c higher storage temperatures reduce data retention time. recommended storage temper- ature is +25 c 25 c. extended duration storage temperatures higher than 65 c degrade reliability. t baketemp bake temperature ? 125 see package label c t baketime bake time see package label ? 72 hours t a ambient temperature with power applied ?40 ? +85 c v dd supply voltage on v dd relative to v ss ?0.5 ? +6.0 v v io dc input voltage v ss ? 0.5 ? v dd + 0.5 v v ioz dc voltage applied to tristate v ss ? 0.5 ? v dd + 0.5 v i mio maximum current into any port pin ?25 ? +50 ma i maio maximum current into any port pin configured as analog driver ?50 ? +50 ma esd electrostatic discharge voltage 2000 ? ? v human body model esd. lu latch-up current ? ? 200 ma [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 20 of 61 operating temperature dc electrical characteristics dc chip-level specifications ta b l e 1 3 lists guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 12. operating temperature symbol description min typ max unit notes t a ambient temperature ?40 ? +85 c t j junction temperature ?40 ? +100 c the temperature rise from ambient to junction is package specific. see ?thermal impedances? on page 49. you must limit the power consumption to comply with this requirement. table 13. dc chip-level specifications symbol description min typ max unit s notes v dd supply voltage 3.00 ? 5.25 v see dc por, smp, and lvd specifications on page 33 . i dd supply current ? 8 14 ma conditions are 5.0 v, t a = 25 c, cpu = 3 mhz, sysclk doubler disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 0.366 khz. i dd3 supply current ? 5 9 ma conditions are v dd = 3.3 v, t a = 25 c, cpu = 3 mhz, sysclk doubler disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 0.366 khz. i ddp supply current when imo = 6 mhz using slimo mode. ? 2 3 ma conditions are v dd = 3.3 v, t a = 25 c, cpu = 0.75 mhz, sysclk doubler disabled, vc1 = 0.375 mhz, vc2 = 23.44 khz, vc3 = 0.09 khz. i sb sleep (mode) current with por, lvd, sleep timer, wdt, and internal slow oscillator active. ? 3 10 a conditions are with internal slow speed oscillator, v dd = 3.3 v, ?40 c t a 55 c. i sbh sleep (mode) current with por, lvd, sleep timer, wdt, and internal slow oscillator active. ? 4 25 a conditions are with internal slow speed oscillator, v dd = 3.3 v, 55 c < t a 85 c. i sbxtl sleep (mode) current with por, lvd, sleep timer, wdt, internal slow oscillator, and 32 khz crystal oscillator active. ? 4 12 a conditions are with properly loaded, 1 w max, 32.768 khz crystal. v dd = 3.3 v, ?40 c t a 55 c. i sbxtlh sleep (mode) current with por, lvd, sleep timer, wdt, and 32 khz crystal oscillator active. ? 5 27 a conditions are with properly loaded, 1 w max, 32.768 khz crystal. v dd = 3.3 v, 55 c < t a 85 c. v ref reference voltage (bandgap) 1.28 1.3 1.32 v trimmed for appropriate v dd . [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 21 of 61 dc gpio specifications ta b l e 1 4 lists guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. dc operational amplifier specifications ta b l e 1 5 and table 16 list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. the operational amplifier is a component of both the anal og continuous time psoc blocks a nd the analog swit ched cap psoc blocks. the guaranteed spec ifications are measured in the anal og continuous time psoc block. ty pical parameters apply to 5 v at 25 c and are for design guidance only. table 14. dc gpio specifications symbol description min typ max unit notes r pu pull-up resistor 4 5.6 8 k r pd pull-down resistor 4 5.6 8 k v oh high output level v dd ? 1.0 ? ? v i oh = 10 ma, v dd = 4.75 to 5.25 v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). 80 ma maximum combined i oh budget. v ol low output level ? ? 0.75 v i ol = 25 ma, v dd = 4.75 to 5.25 v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). 150 ma maximum combined i ol budget. i oh high level source current 10 ? ? ma v oh = v dd ? 1.0 v, see the limitations of the total current in the note for v oh i ol low level sink current 25 ? ? ma v ol = 0.75 v, see the limitations of the total current in the note for v ol v il input low level ? ? 0.8 v v dd = 3.0 to 5.25 v ih input high level 2.1 ? ? v v dd = 3.0 to 5.25 v h input hysteresis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. temp = 25 c. c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. temp = 25 c. table 15. 5-v dc operational amplifier specifications symbol description min typ max unit notes v osoa input offset voltage (absolute value) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 1.6 1.6 1.6 1.6 1.6 1.6 10 10 10 10 10 10 mv mv mv mv mv mv tcv osoa average input offset voltage drift ? 4 23 v/c i eboa input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. te m p = 2 5 c [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 22 of 61 v cmoa common mode voltage range (all cases, except power = high, opamp bias = high) common mode voltage range (power = high, opamp bias = high) 0 0.5 ? ? v dd v dd ? 0.5 v v the common-mode input voltage range is measured through an analog output buffer. the specification includes the limitations imposed by the characteristics of the analog output buffer. cmrroa common mode rejection ratio 60 ? ? db goloa open loop gain 80 ? ? db v ohighoa high output voltage swing (internal signals) v dd ? 0.01 ? ? v v olowoa low output voltage swing (internal signals) ? ? 0.1 v i soa supply current (including associated agnd buffer) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 150 300 600 1200 2400 4600 200 400 800 1600 3200 6400 a a a a a a psrr oa supply voltage rejection ratio 67 80 ? db v ss v in (v dd ? 2.25) or (v dd ? 1.25 v) v in v dd . table 15. 5-v dc operational amplifier specifications (continued) symbol description min typ max unit notes table 16. 3.3-v dc operatio nal amplifier specifications symbol description min typ max unit notes v osoa input offset voltage (absolute value) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 1.4 1.4 1.4 1.4 1.4 ? 10 10 10 10 10 ? mv mv mv mv mv mv power = high, opamp bias = high setting is not allowed for 3.3 v v dd operation. tcv osoa average input offset voltage drift ? 7 40 v/c i eboa input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25 c v cmoa common mode voltage range 0 ? v dd v the common-mode input voltage range is measured through an analog output buffer. the specification includes the limitations imposed by the characteristics of the analog output buffer. cmrr oa common mode rejection ratio 60 ? ? db g oloa open loop gain 80 ? ? db v ohighoa high output voltage swing (internal signals) v dd ? 0.01 ? ? v [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 23 of 61 dc low-power comparator specifications ta b l e 1 7 lists guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, 3.0 v to 3.6 v and ?40 c t a 85 c, or 2.4 v to 3.0 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v at 25 c and are for design guidance only. dc analog output bu ffer specifications ta b l e 1 8 and table 19 list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. v olowoa low output voltage swing (internal signals) ? ? 0.01 v i soa supply current (including associated agnd buffer) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 150 300 600 1200 2400 ? 200 400 800 1600 3200 ? a a a a a a power = high, opamp bias = high setting is not allowed for 3.3 v v dd operation. psrr oa supply voltage rejection ratio 54 80 ? db v ss v in (v dd ? 2.25) or (v dd ? 1.25 v) v in v dd table 16. 3.3-v dc operatio nal amplifier specifications (continued) symbol description min typ max unit notes table 17. dc low-power comparator specifications symbol description min typ max unit v reflpc low-power comparator (lpc) reference voltage range 0.2 ? v dd ? 1 v i slpc lpc supply current ? 10 40 a v oslpc lpc voltage offset ? 2.5 30 mv table 18. 5-v dc analog output buffer specifications symbol description min typ max unit notes v osob input offset voltage (absolute value) power = low, opamp bias = low power = low, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? 3.2 3.2 3.2 3.2 18 18 18 18 mv mv mv mv tcv osob average input offset voltage drift ? 5.5 26 v/c v cmob common-mode input voltage range 0.5 ? v dd ? 1.0 v r outob output resistance power = low power = high ? ? ? ? 1 1 v ohighob high output voltage swing (load = 32 ohms to v dd /2) power = low power = high 0.5 v dd + 1.3 0.5 v dd + 1.3 ? ? ? ? v v v olowob low output voltage swing (load = 32 ohms to v dd /2) power = low power = high ? ? ? ? 0.5 v dd ? 1.3 0.5 v dd ? 1.3 v v [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 24 of 61 i sob supply current including bias cell (no load) power = low power = high ? ? 1.1 2.6 2 5 ma ma psrr ob supply voltage rejection ratio 40 64 db c l load capacitance ? ? 200 pf this specification applies to the external circuit driven by the analog output buffer. table 19. 3.3-v dc analog output buffer specifications symbol description min typ max unit notes v osob input offset voltage (absolute value) power = low, opamp bias = low power = low, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? 3.2 3.2 6 6 20 20 25 25 mv mv mv mv high power setting is not recommended. tcv osob average input offset voltage drift power = low, opamp bias = low power = low, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? 8 8 12 12 32 32 41 41 v/c v/c v/c v/c high power setting is not recommended. v cmob common-mode input voltage range 0.5 ? v dd ? 1.0 v r outob output resistance power = low power = high ? ? ? ? 10 10 w w v ohighob high output voltage swing (load = 32 ohms to v dd /2) power = low power = high 0.5 v dd + 1.0 0.5 v dd + 1.0 ? ? ? ? v v v olowob low output voltage swing (load = 32 ohms to v dd /2) power = low power = high ? ? ? ? 0.5 v dd ? 1.0 0.5 v dd ? 1.0 v v i sob supply current including bias cell (no load) power = low power = high ? ? 0.8 2.0 1 5 ma ma psrr ob supply voltage rejection ratio 60 64 ? db c l load capacitance ? ? 200 pf this specification applies to the external circuit driven by the analog output buffer. table 18. 5-v dc analog output buffer specifications (continued) symbol description min typ max unit notes [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 25 of 61 dc switch mode pump specifications ta b l e 2 0 lists guaranteed maximum and minimum specifications for th e voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 20. dc switch mode pump (smp) specifications symbol description min typ max unit notes v pump 5 v 5 v output voltage at v dd from pump 4.75 5.0 5.25 v configured as in note 10. average, neglecting ripple. smp trip voltage is set to 5.0 v v pump 3 v 3 v output voltage at v dd from pump 3.00 3.25 3.60 v configured as in note 10. average, neglecting ripple. smp trip voltage is set to 3.25 v i pump available output current v bat = 1.5 v, v pump = 3.25 v v bat = 1.8 v, v pump = 5.0 v 8 5 ? ? ? ? ma ma configured as in note 10 smp trip voltage is set to 3.25 v smp trip voltage is set to 5.0 v v bat 5 v input voltage range from battery 1.8 ? 5.0 v configured as in note 10. smp trip voltage is set to 5.0 v v bat 3 v input voltage range from battery 1.0 ? 3.3 v configured as in note 10. smp trip voltage is set to 3.25 v v batstart minimum input voltage from battery to start pump 1.2 ? ? v configured as in note 10.0 c t a 100. 1.25 v at t a = ?40 c v pump_line line regulation (over v bat range) ? 5 ? %v o configured as in note 10. v o is the ?v dd value for pump trip? specified by the vm[2:0] setting in the dc por and lvd specification, table 24, ?dc por, smp, and lvd specifications,? on page 33 v pump_load load regulation ? 5 ? %v o configured as in note 10. v o is the ?v dd value for pump trip? specified by the vm[2:0] setting in table 24, ?dc por, smp, and lvd specifica- tions,? on page 33 v pump_ripple output voltage ripple (depends on capacitor/load) ? 100 ? mvpp configured as in note 10. load is 5 ma e 3 efficiency 35 50 ? % configured as in note 10. load is 5 ma. smp trip voltage is set to 3.25 v f pump switching frequency ? 1.4 ? mhz dc pump switching duty cycle ? 50 ? % note 10. l 1 = 2 h inductor, c 1 = 10 f capacitor, d 1 = schottky diode. see figure 11 . [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 26 of 61 figure 11. basic switch mode pump circuit dc analog reference specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ta 85 c, or 3.0 v to 3.6 v and ?40 c ta 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. the guaranteed specifications for refhi a nd reflo are measured through the analog continuous time psoc blocks. the power levels for refhi and reflo refer to the analog reference control register. agnd is measured at p2[4] in agnd bypass mode. each analog continuous time psoc block adds a maximum of 10 mv additional offset error to guaranteed agnd specifications from the local agnd buffer. reference control power can be set to medium or high unless otherwise noted. note avoid using p2[4] for digital signaling when using an analog reso urce that depends on the analog reference. some coupling of the digital signal may appear on the agnd. battery c1 d1 + psoc vdd vss smp v bat v pump l 1 table 21. 5-v dc analog reference specifications reference arf_cr[5:3] reference power settings symbol reference description min typ max unit 0b000 refpower = high opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.228 v dd /2 + 1.290 v dd /2 + 1.352 v v agnd agnd v dd /2 v dd /2 ? 0.078 v dd /2 ? 0.007 v dd /2 + 0.063 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.336 v dd /2 ? 1.295 v dd /2 ? 1.250 v refpower = high opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 1.224 v dd /2 + 1.293 v dd /2 + 1.356 v v agnd agnd v dd /2 v dd /2 ? 0.056 v dd /2 ? 0.005 v dd /2 + 0.043 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.338 v dd /2 ? 1.298 v dd /2 ? 1.255 v refpower = med opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.226 v dd /2 + 1.293 v dd /2 + 1.356 v v agnd agnd v dd /2 v dd /2 ? 0.057 v dd /2 ? 0.006 v dd /2 + 0.044 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.337 v dd /2 ? 1.298 v dd /2 ? 1.256 v refpower = med opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 1.226 v dd /2 + 1.294 v dd /2 + 1.359 v v agnd agnd v dd /2 v dd /2 ? 0.047 v dd /2 ? 0.004 v dd /2 + 0.035 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.338 v dd /2 ? 1.299 v dd /2 ? 1.258 v [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 27 of 61 0b001 refpower = high opamp bias = high v refhi ref high p2[4] + p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.085 p2[4] + p2[6] ? 0.016 p2[4] + p2[6] + 0.044 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.022 p2[4] ? p2[6] + 0.010 p2[4] ? p2[6] + 0.055 v refpower = high opamp bias = low v refhi ref high p2[4] + p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.077 p2[4] + p2[6] ? 0.010 p2[4] + p2[6] + 0.051 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.022 p2[4] ? p2[6] + 0.005 p2[4] ? p2[6] + 0.039 v refpower = med opamp bias = high v refhi ref high p2[4] + p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.070 p2[4] + p2[6] ? 0.010 p2[4] + p2[6] + 0.050 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.022 p2[4] ? p2[6] + 0.005 p2[4] ? p2[6] + 0.039 v refpower = med opamp bias = low v refhi ref high p2[4] + p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.070 p2[4] + p2[6] ? 0.007 p2[4] + p2[6] + 0.054 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.022 p2[4] ? p2[6] + 0.002 p2[4] ? p2[6] + 0.032 v 0b010 refpower = high opamp bias = high v refhi ref high v dd v dd ? 0.037 v dd ? 0.009 v dd v v agnd agnd v dd /2 v dd /2 ? 0.061 v dd /2 ? 0.006 v dd /2 + 0.047 v v reflo ref low v ss v ss v ss + 0.007 v ss + 0.028 v refpower = high opamp bias = low v refhi ref high v dd v dd ? 0.039 v dd ? 0.006 v dd v v agnd agnd v dd /2 v dd /2 ? 0.049 v dd /2 ? 0.005 v dd /2 + 0.036 v v reflo ref low v ss v ss v ss + 0.005 v ss + 0.019 v refpower = med opamp bias = high v refhi ref high v dd v dd ? 0.037 v dd ? 0.007 v dd v v agnd agnd v dd /2 v dd /2 ? 0.054 v dd /2 ? 0.005 v dd /2 + 0.041 v v reflo ref low v ss v ss v ss + 0.006 v ss + 0.024 v refpower = med opamp bias = low v refhi ref high v dd v dd ? 0.042 v dd ? 0.005 v dd v v agnd agnd v dd /2 v dd /2 ? 0.046 v dd /2 ? 0.004 v dd /2 + 0.034 v v reflo ref low v ss v ss v ss + 0.004 v ss + 0.017 v table 21. 5-v dc analog reference specifications (continued) reference arf_cr[5:3] reference power settings symbol reference description min typ max unit [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 28 of 61 0b011 refpower = high opamp bias = high v refhi ref high 3 bandgap 3.788 3.891 3.986 v v agnd agnd 2 bandgap 2.500 2.604 3.699 v v reflo ref low bandgap 1.257 1.306 1.359 v refpower = high opamp bias = low v refhi ref high 3 bandgap 3.792 3.893 3.982 v v agnd agnd 2 bandgap 2.518 2.602 2.692 v v reflo ref low bandgap 1.256 1.302 1.354 v refpower = med opamp bias = high v refhi ref high 3 bandgap 3.795 3.894 3.993 v v agnd agnd 2 bandgap 2.516 2.603 2.698 v v reflo ref low bandgap 1.256 1.303 1.353 v refpower = med opamp bias = low v refhi ref high 3 bandgap 3.792 3.895 3.986 v v agnd agnd 2 bandgap 2.522 2.602 2.685 v v reflo ref low bandgap 1.255 1.301 1.350 v 0b100 refpower = high opamp bias = high v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.495 ? p2[6] 2.586 ? p2[6] 2.657 ? p2[6] v v agnd agnd 2 bandgap 2.502 2.604 2.719 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.531 ? p2[6] 2.611 ? p2[6] 2.681 ? p2[6] v refpower = high opamp bias = low v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.500 ? p2[6] 2.591 ? p2[6] 2.662 ? p2[6] v v agnd agnd 2 bandgap 2.519 2.602 2.693 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.530 ? p2[6] 2.605 ? p2[6] 2.666 ? p2[6] v refpower = med opamp bias = high v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.503 ? p2[6] 2.592 ? p2[6] 2.662 ? p2[6] v v agnd agnd 2 bandgap 2.517 2.603 2.698 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.529 ? p2[6] 2.606 ? p2[6] 2.665 ? p2[6] v refpower = med opamp bias = low v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.505 ? p2[6] 2.594 ? p2[6] 2.665 ? p2[6] v v agnd agnd 2 bandgap 2.525 2.602 2.685 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.528 ? p2[6] 2.603 ? p2[6] 2.661 ? p2[6] v table 21. 5-v dc analog reference specifications (continued) reference arf_cr[5:3] reference power settings symbol reference description min typ max unit [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 29 of 61 0b101 refpower = high opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.222 p2[4] + 1.290 p2[4] + 1.343 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.331 p2[4] ? 1.295 p2[4] ? 1.254 v refpower = high opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.226 p2[4] + 1.293 p2[4] + 1.347 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.331 p2[4] ? 1.298 p2[4] ? 1.259 v refpower = med opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.227 p2[4] + 1.294 p2[4] + 1.347 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.331 p2[4] ? 1.298 p2[4] ? 1.259 v refpower = med opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.228 p2[4] + 1.295 p2[4] + 1.349 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.332 p2[4] ? 1.299 p2[4] ? 1.260 v 0b110 refpower = high opamp bias = high v refhi ref high 2 bandgap 2.535 2.598 2.644 v v agnd agnd bandgap 1.227 1.305 1.398 v v reflo ref low v ss v ss v ss + 0.009 v ss + 0.038 v refpower = high opamp bias = low v refhi ref high 2 bandgap 2.530 2.598 2.643 v v agnd agnd bandgap 1.244 1.303 1.370 v v reflo ref low v ss v ss v ss + 0.005 v ss + 0.024 v refpower = med opamp bias = high v refhi ref high 2 bandgap 2.532 2.598 2.644 v v agnd agnd bandgap 1.239 1.304 1.380 v v reflo ref low v ss v ss v ss + 0.006 v ss + 0.026 v refpower = med opamp bias = low v refhi ref high 2 bandgap 2.528 2.598 2.645 v v agnd agnd bandgap 1.249 1.302 1.362 v v reflo ref low v ss v ss v ss + 0.004 v ss + 0.018 v 0b111 refpower = high opamp bias = high v refhi ref high 3.2 bandgap 4.041 4.155 4.234 v v agnd agnd 1.6 bandgap 1.998 2.083 2.183 v v reflo ref low v ss v ss v ss + 0.010 v ss + 0.038 v refpower = high opamp bias = low v refhi ref high 3.2 bandgap 4.047 4.153 4.236 v v agnd agnd 1.6 bandgap 2.012 2.082 2.157 v v reflo ref low v ss v ss v ss + 0.006 v ss + 0.024 v refpower = med opamp bias = high v refhi ref high 3.2 bandgap 4.049 4.154 4.238 v v agnd agnd 1.6 bandgap 2.008 2.083 2.165 v v reflo ref low v ss v ss v ss + 0.006 v ss + 0.026 v refpower = med opamp bias = low v refhi ref high 3.2 bandgap 4.047 4.154 4.238 v v agnd agnd 1.6 bandgap 2.016 2.081 2.150 v v reflo ref low v ss v ss v ss + 0.004 v ss + 0.018 v table 21. 5-v dc analog reference specifications (continued) reference arf_cr[5:3] reference power settings symbol reference description min typ max unit [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 30 of 61 table 22. 3.3-v dc analog reference specifications reference arf_cr[5:3] reference power settings symbol reference description min typ max unit 0b000 refpower = high opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.225 v dd /2 + 1.292 v dd /2 + 1.361 v v agnd agnd v dd /2 v dd /2 ? 0.067 v dd /2 ? 0.002 v dd /2 + 0.063 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.35 v dd /2 ? 1.293 v dd /2 ? 1.210 v refpower = high opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 1.218 v dd /2 + 1.294 v dd /2 + 1.370 v v agnd agnd v dd /2 v dd /2 ? 0.038 v dd /2 ? 0.001 v dd /2 + 0.035 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.329 v dd /2 ? 1.296 v dd /2 ? 1.259 v refpower = med opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.221 v dd /2 + 1.294 v dd /2 + 1.366 v v agnd agnd v dd /2 v dd /2 ? 0.050 v dd /2 ? 0.002 v dd /2 + 0.046 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.331 v dd /2 ? 1.296 v dd /2 ? 1.260 v refpower = med opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 1.226 v dd /2 + 1.295 v dd /2 + 1.365 v v agnd agnd v dd /2 v dd /2 ? 0.028 v dd /2 ? 0.001 v dd /2 + 0.025 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.329 v dd /2 ? 1.297 v dd /2 ? 1.262 v 0b001 refpower = high opamp bias = high v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.098 p2[4] + p2[6] ? 0.018 p2[4] + p2[6] + 0.055 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.055 p2[4] ? p2[6] + 0.013 p2[4] ? p2[6] + 0.086 v refpower = high opamp bias = low v refhi ref high p2[4] + p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.082 p2[4] + p2[6] ? 0.011 p2[4] + p2[6] + 0.050 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.037 p2[4] ? p2[6] + 0.006 p2[4] ? p2[6] + 0.054 v refpower = med opamp bias = high v refhi ref high p2[4] + p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.079 p2[4] + p2[6] ? 0.012 p2[4] + p2[6] + 0.047 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.038 p2[4] ? p2[6] + 0.006 p2[4] ? p2[6] + 0.057 v refpower = med opamp bias = low v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.080 p2[4] + p2[6] ? 0.008 p2[4] + p2[6] + 0.055 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.032 p2[4] ? p2[6] + 0.003 p2[4] ? p2[6] + 0.042 v [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 31 of 61 0b010 refpower = high opamp bias = high v refhi ref high v dd v dd ? 0.06 v dd ? 0.010 v dd v v agnd agnd v dd /2 v dd /2 ? 0.05 v dd /2 ? 0.002 v dd /2 + 0.040 v v reflo ref low vss vss vss + 0.009 vss + 0.056 v refpower = high opamp bias = low v refhi ref high v dd v dd ? 0.060 v dd ? 0.006 v dd v v agnd agnd v dd /2 v dd /2 ? 0.028 v dd /2 ? 0.001 v dd /2 + 0.025 v v reflo ref low vss vss vss + 0.005 vss + 0.034 v refpower = med opamp bias = high v refhi ref high v dd v dd ? 0.058 v dd ? 0.008 v dd v v agnd agnd v dd /2 v dd /2 ? 0.037 v dd /2 ? 0.002 v dd /2 + 0.033 v v reflo ref low vss vss vss + 0.007 vss + 0.046 v refpower = med opamp bias = low v refhi ref high v dd v dd ? 0.057 v dd ? 0.006 v dd v v agnd agnd v dd /2 v dd /2 ? 0.025 v dd /2 ? 0.001 v dd /2 + 0.022 v v reflo ref low vss vss vss + 0.004 vss + 0.030 v 0b011 all power settings. not allowed for 3.3 v ? ? ? ? ? ? ? 0b100 all power settings. not allowed for 3.3 v ? ? ? ? ? ? ? 0b101 refpower = high opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.213 p2[4] + 1.291 p2[4] + 1.367 v v agnd agnd p2[4] p2[4] p2[4] p2[4] v v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.333 p2[4] ? 1.294 p2[4] ? 1.208 v refpower = high opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.217 p2[4] + 1.294 p2[4] + 1.368 v v agnd agnd p2[4] p2[4] p2[4] p2[4] v v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.320 p2[4] ? 1.296 p2[4] ? 1.261 v refpower = med opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.217 p2[4] + 1.294 p2[4] + 1.369 v v agnd agnd p2[4] p2[4] p2[4] p2[4] v v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.322 p2[4] ? 1.297 p2[4] ? 1.262 v refpower = med opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.219 p2[4] + 1.295 p2[4] + 1.37 v v agnd agnd p2[4] p2[4] p2[4] p2[4] v v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.324 p2[4] ? 1.297 p2[4] ? 1.262 v table 22. 3.3-v dc analog reference specifications (continued) reference arf_cr[5:3] reference power settings symbol reference description min typ max unit [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 32 of 61 dc analog psoc block specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. 0b110 refpower = high opamp bias = high v refhi ref high 2 bandgap 2.507 2.598 2.698 v v agnd agnd bandgap 1.203 1.307 1.424 v v reflo ref low vss vss vss + 0.012 vss + 0.067 v refpower = high opamp bias = low v refhi ref high 2 bandgap 2.516 2.598 2.683 v v agnd agnd bandgap 1.241 1.303 1.376 v v reflo ref low vss vss vss + 0.007 vss + 0.040 v refpower = med opamp bias = high v refhi ref high 2 bandgap 2.510 2.599 2.693 v v agnd agnd bandgap 1.240 1.305 1.374 v v reflo ref low vss vss vss + 0.008 vss + 0.048 v refpower = med opamp bias = low v refhi ref high 2 bandgap 2.515 2.598 2.683 v v agnd agnd bandgap 1.258 1.302 1.355 v v reflo ref low vss vss vss + 0.005 vss + 0.03 v 0b111 all power settings. not allowed for 3.3 v. ? ? ? ? ? ? ? table 23. dc analog psoc block specifications symbol description min typ max unit notes r ct resistor unit value (continuous time) ? 12.2 ? k c sc capacitor unit value (switch cap) ? 80 ? ff table 22. 3.3-v dc analog reference specifications (continued) reference arf_cr[5:3] reference power settings symbol reference description min typ max unit [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 33 of 61 dc por, smp, and lvd specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 24. dc por, smp, and lvd specifications symbol description min typ max units notes v ppor0r v ppor1r v ppor2r v dd value for ppor trip (positive ramp) porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? 2.91 4.39 4.55 ? v v v v ppor0 v ppor1 v ppor2 v dd value for ppor trip (negative ramp) porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? 2.82 4.39 4.55 ? v v v v ph0 v ph1 v ph2 ppor hysteresis porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? ? ? 92 0 0 ? ? ? mv mv mv v lvd0 v lvd1 v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 v lvd7 v dd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 2.98 [11] 3.08 3.20 4.08 4.57 4.74 [12] 4.82 4.91 v v v v v v v v v pump0 v pump1 v pump2 v pump3 v pump4 v pump5 v pump6 v pump7 v dd value for smp trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.96 3.03 3.18 4.11 4.55 4.63 4.72 4.90 3.02 3.10 3.25 4.19 4.64 4.73 4.82 5.00 3.08 3.16 3.32 4.28 4.74 4.82 4.91 5.10 v v v v v v v v notes 11. always greater than 50 mv above ppor (porlev = 00) for falling supply. 12. always greater than 50 mv above ppor (porlev = 10) for falling supply. [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 34 of 61 dc programming specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. dc i 2 c specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 25. dc programming specifications symbol description min typ max units notes v ddp v dd for programming and erase 4.5 5 5.5 v this specification applies to the functional requirements of external programmer tools. v ddlv low v dd for verify 33.13.2 v this specification applies to the functional requirements of external programmer tools. v ddhv high v dd for verify 5.1 5.2 5.3 v this specification applies to the functional requirements of external programmer tools. v ddiwrite supply voltage for flash write operation 3.15 5.25 v this specification applies to this device when it is executing internal flash writes. i ddp supply current during programming or verify ? 10 30 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.2 ? ? v i ilp input current when applying vilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull-down resistor i ihp input current when applying vihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull-down resistor v olv output low voltage during programming or verify ? ? v ss + 0.75 v v ohv output high voltage during programming or verify v dd ? 1.0 ? v dd v flash enpb flash endurance (per block) 50,000 [13] ? ? ? erase/write cycles per block flash ent flash endurance (total) [14] 1,800,000 ? ? ? erase/write cycles flash dr flash data retention 10 ? ? years notes 13. the 50,000 cycle flash endurance per block is only guaranteed if the flash is operating within one voltage range. voltage ra nges are 3.0 v to 3.6 v and 4.75 v to 5.25 v. 14. a maximum of 36 50,000 block endurance cycles is allowed. this may be bala nced between operations on 36 1 blocks of 50,0 00 maximum cycles each, 36 2 blocks of 25,000 maximum cycles each, or 36 4 blocks of 12,500 maximum cycles each (to lim it the total number of cycle s to 36 50,000 and that no single block ever sees more than 50,000 cycles). for the full industrial range, the user must employ a temperature sensor user module (flashtemp) and feed the result to the tem perature argument before writing. refer to the flash apis application note design aids ? reading and writing psoc ? flash ? an2015 for more information. 15. all gpios meet the dc gpio v il and v ih specifications found in the dc gpio specific ations sections.the i 2 c gpio pins also meet the mentioned specs. table 26. dc i 2 c specifications parameter description min typ max units notes v ili2c [15] input low level ? ? 0.3 v dd v 3.0 v v dd 3.6 v ? ? 0.25 v dd v4.75 v v dd 5.25 v v ihi2c [15] input high level 0.7 v dd ? ? v 3.0 v v dd 5.25 v [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 35 of 61 ac electrical characteristics ac chip-level specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. note see the individual user module datasheets for inform ation on maximum frequencies for user modules. table 27. ac chip-level specifications symbol description min typ max units notes f imo24 internal main oscillator (imo) frequency for 24 mhz 23.4 24 24.6 [16,17] mhz trimmed for 5 v or 3.3 v operation using factory trim values. see figure 10 on page 19 . slimo mode = 0. f imo6 imo frequency for 6 mhz 5.5 6 6.5 [16,17] mhz trimmed for 5 v or 3.3 v operation using factory trim values. see figure 10 on page 19 . slimo mode = 1. f cpu1 cpu frequency (5 v nominal) 0.0914 24 24.6 [16] mhz slimo mode = 0. f cpu2 cpu frequency (3.3 v nominal) 0.0914 12 12.3 [17] mhz slimo mode = 0. f 48m digital psoc block frequency 0 48 49.2 [16,18] mhz refer to ac digital block specifications on page 40 . f 24m digital psoc block frequency 0 24 24.6 [18] mhz f 32k1 internal low speed oscillator frequency 15 32 64 khz f 32k2 external crystal oscillator ? 32.768 ? khz accuracy is capacitor and crystal dependent. 50% duty cycle f 32k_u internal low speed oscillator (ilo) untrimmed frequency 5 ? 100 khz after a reset and before the m8c starts to run, the ilo is not trimmed. see the system resets section of the psoc technical reference manual for details on this timing f pll pll frequency ? 23.986 ? mhz a multiple (x732) of crystal frequency t pllslew pll lock time 0.5 ? 10 ms t pllslewlow pll lock time for low gain setting 0.5 ? 50 ms t os external crystal oscillator startup to 1% ? 250 500 ms t osacc external crystal oscillator startup to 100 ppm ? 300 600 ms the crystal oscillator frequency is within 100 ppm of its final value by the end of the t osacc period. correct operation assumes a properly loaded 1 w maximum drive level 32.768 khz crystal. 3.0 v v dd 5.5 v, ?40 c t a 85 c. t xrst external reset pulse width 10 ? ? s dc24m 24 mhz duty cycle 40 50 60 % dc ilo internal low speed oscillator duty cycle 20 50 80 % step24m 24 mhz trim step size ? 50 ? khz fout48m 48 mhz output frequency 46.8 48.0 49.2 [16, 17] mhz trimmed. using factory trim values notes 16. 4.75 v < v dd < 5.25 v. 17. 3.0 v < v dd < 3.6 v. see application note adjusting psoc ? trims for 3.3 v and 2.7 v operation ? an2012 for information on trimming for operation at 3.3 v. 18. see the individual user module datasheets for in formation on maximum frequencies for user modules [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 36 of 61 figure 12. pll lock timing diagram figure 13. pll lock for low gain setting timing diagram figure 14. external crystal oscillator startup timing diagram f max maximum frequency of signal on row input or row output. ? ? 12.3 mhz sr power_up power supply slew rate ? ? 250 v/ms v dd slew rate during power-up t powerup time from end of por to cpu executing code ? 16 100 ms power-up from 0 v. see the system resets section of the psoc technical reference manual tjit_imo [19] 24 mhz imo cycle-to-cycle jitter (rms) ? 200 700 ps n = 32 24 mhz imo long term n cycle-to-cycle jitter (rms) ? 300 900 24 mhz imo period jitter (rms) ? 100 400 tjit_pll [19] 24 mhz imo cycle-to-cycle jitter (rms) ? 200 800 ps n = 32 24 mhz imo long term n cycle-to-cycle jitter (rms) ? 300 1200 24 mhz imo period jitter (rms) ? 100 700 table 27. ac chip-level specifications (continued) symbol description min typ max units notes note 19. refer to cypress jitter specifications application note, understanding datasheet jitter specificat ions for cypress timing products ? an5054 for more information. 24 mhz f pll pll enable t pllslew pll gain 0 24 mhz f pll pll enable t pllslewlow pll gain 1 32 khz f 32k2 32k select t os [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 37 of 61 ac general purpose i/o specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. figure 15. gpio timing diagram ac operational amplifier specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. settling times, slew rates, and gain bandwidth are based on the analog continuous time psoc block. power = high and opamp bias = high is not supported at 3.3 v. table 28. ac gpio specifications symbol description min typ max unit notes f gpio gpio operating frequency 0 ? 12.3 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 3 ? 18 ns v dd = 4.75 to 5.25 v, 10% to 90% tfallf fall time, normal strong mode, cload = 50 pf 2 ? 18 ns v dd = 4.75 to 5.25 v, 10% to 90% trises rise time, slow strong mode, cload = 50 pf 10 27 ? ns v dd = 3 to 5.25 v, 10% to 90% tfalls fall time, slow strong mode, cload = 50 pf 10 22 ? ns v dd = 3 to 5.25 v, 10% to 90% tfallf tfalls tris ef trises 90% 10% gpio pin output voltage table 29. 5-v ac operational amplifier specifications symbol description min typ max unit t roa rising settling time to 0.1% for a 1 v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 3.9 0.72 0.62 s s s t soa falling settling time to 0.1% for a 1 v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 5.9 0.92 0.72 s s s sr roa rising slew rate (20% to 80%) of a 1 v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.15 1.7 6.5 ? ? ? ? ? ? v/s v/s v/s sr foa falling slew rate (20% to 80%) of a 1 v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.01 0.5 4.0 ? ? ? ? ? ? v/s v/s v/s bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.75 3.1 5.4 ? ? ? ? ? ? mhz mhz mhz e noa noise at 1 khz (power = medium, opamp bias = high) ? 100 ? nv/rt-hz [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 38 of 61 when bypassed by a capacitor on p2[4], the noise of the analog ground signal distributed to each block is reduced by a factor o f up to 5 (14 db). this is at frequencies above the corner frequency defined by the on-chip 8.1 k resistance and the external capaci tor. figure 16. typical agnd noise with p2[4] bypass at low frequencies, the opamp noise is proportional to 1/ f, power independent, and determined by device geometry. at high frequencies, increased power level reduces the noise spectrum level. table 30. 3.3-v ac operatio nal amplifier specifications symbol description min typ max units t roa rising settling time to 0.1% of a 1 v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high ? ? ? ? 3.92 0.72 s s t soa falling settling time to 0.1% of a 1 v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high ? ? ? ? 5.41 0.72 s s sr roa rising slew rate (20% to 80%) of a 1 v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high 0.31 2.7 ? ? ? ? v/s v/s sr foa falling slew rate (20% to 80%) of a 1 v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high 0.24 1.8 ? ? ? ? v/s v/s bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high 0.67 2.8 ? ? ? ? mhz mhz e noa noise at 1 khz (power = medium, opamp bias = high) ? 100 ? nv/rt-hz ? 100 1000 10000 0.001 0.01 0.1 1 10 100 fr eq (khz ) nv/rthz 0 0.01 0.1 1.0 10 [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 39 of 61 figure 17. typical opamp noise ac low-power comparator specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, 3.0 v to 3.6 v and ?40 c t a 85 c, or 2.4 v to 3.0 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v at 25 c and are for design guidance only. table 31. ac low-power comparator specifications symbol description min typ max unit notes t rlpc lpc response time ? ? 50 s 50 mv overdrive comparator reference set within v reflpc 10 100 1000 10000 0.001 0.01 0.1 1 10 100 freq (khz) nv/rthz ph_ bh ph_ bl pm_bl pl_ bl [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 40 of 61 ac digital block specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 32. ac digital block specifications function description min typ max unit notes all functions block input clock frequency v dd 4.75 v ? ? 49.2 mhz v dd < 4.75 v ? ? 24.6 mhz timer input clock frequency no capture, v dd 4.75 v ? ? 49.2 mhz no capture, v dd < 4.75 v ? ? 24.6 mhz with capture ? ? 24.6 mhz capture pulse width 50 [20] ??ns counter input clock frequency no enable input, v dd 4.75 v ? ? 49.2 mhz no enable input, v dd < 4.75 v ? ? 24.6 mhz with enable input ? ? 24.6 mhz enable input pulse width 50 [20] ??ns dead band kill pulse width asynchronous restart mode 20 ? ? ns synchronous restart mode 50 [20] ??ns disable mode 50 [20] ??ns input clock frequency v dd 4.75 v ? ? 49.2 mhz v dd < 4.75 v ? ? 24.6 mhz crcprs (prs mode) input clock frequency v dd 4.75 v ? ? 49.2 mhz v dd < 4.75 v ? ? 24.6 mhz crcprs (crc mode) input clock frequency ? ? 24.6 mhz spim input clock frequency ? ? 8.2 mhz the spi serial clock (sclk) frequency is equal to the input clock frequency divided by 2 spis input clock (sclk) frequency ? ? 4.1 mhz the input clock is the spi sclk in spis mode width of ss_negated between transmissions 50 [20] ??ns transmitter input clock frequency the baud rate is equal to the input clock frequency divided by 8 v dd 4.75 v, 2 stop bits ? ? 49.2 mhz v dd 4.75 v, 1 stop bit ? ? 24.6 mhz v dd < 4.75 v ? ? 24.6 mhz receiver input clock frequency the baud rate is equal to the input clock frequency divided by 8 v dd 4.75 v, 2 stop bits ? ? 49.2 mhz v dd 4.75 v, 1 stop bit ? ? 24.6 mhz v dd < 4.75 v ? ? 24.6 mhz note 20. 50 ns minimum input pulse width is based on the input synchronizers running at 24 mhz (42 ns nominal period). [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 41 of 61 ac analog output buffer specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. ac external clock specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 33. 5-v ac analog output buffer specifications symbol description min typ max unit t rob rising settling time to 0.1%, 1 v step, 100 pf load power = low power = high ? ? ? ? 4 4 s s t sob falling settling time to 0.1%, 1 v step, 100 pf load power = low power = high ? ? ? ? 3.4 3.4 s s sr rob rising slew rate (20% to 80%), 1 v step, 100 pf load power = low power = high 0.5 0.5 ? ? ? ? v/s v/s sr fob falling slew rate (80% to 20%), 1 v step, 100 pf load power = low power = high 0.55 0.55 ? ? ? ? v/s v/s bw ob small signal bandwidth, 20 mv pp , 3 db bw, 100 pf load power = low power = high 0.8 0.8 ? ? ? ? mhz mhz bw ob large signal bandwidth, 1 v pp , 3 db bw, 100 pf load power = low power = high 300 300 ? ? ? ? khz khz table 34. 3.3-v ac analog output buffer specifications symbol description min typ max unit t rob rising settling time to 0.1%, 1 v step, 100 pf load power = low power = high ? ? ? ? 4.7 4.7 s s t sob falling settling time to 0.1%, 1 v step, 100 pf load power = low power = high ? ? ? ? 4 4 s s sr rob rising slew rate (20% to 80%), 1 v step, 100 pf load power = low power = high 0.36 0.36 ? ? ? ? v/s v/s sr fob falling slew rate (80% to 20%), 1 v step, 100 pf load power = low power = high 0.40 0.40 ? ? ? ? v/s v/s bw ob small signal bandwidth, 20 mv pp , 3 db bw, 100 pf load power = low power = high 0.7 0.7 ? ? ? ? mhz mhz bw ob large signal bandwidth, 1 v pp , 3 db bw, 100 pf load power = low power = high 200 200 ? ? ? ? khz khz table 35. 5-v ac external clock specifications symbol description min typ max unit f oscext frequency 0.093 ?24.6mhz ? high period 20.6 ? 5300 ns ? low period 20.6 ? ?ns ? power-up imo to switch 150 ? ?ms [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 42 of 61 ac programming specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 36. 3.3-v ac external clock specifications symbol description min typ max unit f oscext frequency with cpu clock divide by 1 0.093 ?12.3mhz f oscext frequency with cpu clock divide by 2 or greater 0.186 ?24.6mhz ? high period with cpu clock divide by 1 41.7 ? 5300 ns ? low period with cpu clock divide by 1 41.7 ? ?ns ? power-up imo to switch 150 ? ?s table 37. ac programming specifications symbol description min typ max unit notes t rsclk rise time of sclk 1 ? 20 ns ? t fsclk fall time of sclk 1 ? 20 ns ? t ssclk data setup time to falling edge of sclk 40 ? ? ns ? t hsclk data hold time from falling edge of sclk 40 ? ? ns ? f sclk frequency of sclk 0 ? 8 mhz ? t eraseb flash erase time (block) ? 10 ? ms ? t write flash block write time ? 40 ? ms ? t dsclk data out delay from falling edge of sclk ? ? 45 ns v dd > 3.6 t dsclk3 data out delay from falling edge of sclk ? ? 50 ns 3.0 v dd 3.6 t eraseall flash erase time (bulk) ? 80 ? ms erase all blocks and protection fields at once t program_hot flash block erase + flash block write time ? ? 100 [21] ms 0 c tj 100 c t program_cold flash block erase + flash block write time ? ? 200 [21] ms ?40 c tj 0 c note 21. for the full industrial range, you must employ a temperature sens or user module (flashtemp) and feed the result to the tempe rature argument before writing. refer to the flash apis application note design aids ? reading and writing psoc ? flash ? an2015 for more information. [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 43 of 61 ac i 2 c specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. figure 18. definition for timing for fast/standard mode on the i 2 c bus table 38. ac characteristics of the i 2 c sda and scl pins symbol description standard mode fast mode unit min max min max f scli2c scl clock frequency 0 100 0 400 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ?s t lowi2c low period of the scl clock 4.7 ?1.3 ?s t highi2c high period of the scl clock 4.0 ?0.6 ?s t sustai2c setup time for a repeated start condition 4.7 ?0.6 ?s t hddati2c data hold time 0 ?0 ?s t sudati2c data setup time 250 ?100 [22] ?ns t sustoi2c setup time for stop condition 4.0 ?0.6 ?s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ?s t spi2c pulse width of spikes are suppressed by the input filter. ? ?050ns note 22. a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t su;dat >= 250 ns must then be met. this is the automatic case if the device does not stretc h the low period of the scl signal. if such device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. i2c_sda i2c_scl s sr s p t bufi2c t spi2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c start condition repeated start condition stop condition [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 44 of 61 packaging information this section illustrates the packaging spec ifications for the cy8c29x66 psoc device, along with the thermal impedances for each package and the typical package capacitance on crystal pins. important note emulation tools may require a larger area on the target pc b than the chip's footprint. for a detailed description of the emulation tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com . packaging dimensions figure 19. 28-pin (300-mil) molded dip dimensions in inches[mm] min. max. seating plane 0.260[6.60] 0.295[7.49] 0.090[2.28] 0.110[2.79] 0.055[1.39] 0.065[1.65] 0.015[0.38] 0.020[0.50] 0.015[0.38] 0.060[1.52] 0.120[3.05] 0.140[3.55] 0.009[0.23] 0.012[0.30] 0.310[7.87] 0.385[9.78] 0.290[7.36] 0.325[8.25] 0.030[0.76] 0.080[2.03] 0.115[2.92] 0.160[4.06] 0.140[3.55] 0.190[4.82] 1.345[34.16] 1.385[35.18] 3 min. 1 14 15 28 reference jedec mo-095 part # p28.3 standard pkg. lead free pkg. pz28.3 lead end option see lead end option see lead end option (lead #1, 14, 15 & 28) package weight: 2.15gms 51-85014 *e [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 45 of 61 figure 20. 28-pin (210-mil) ssop figure 21. 28-pin (300-mil) soic 51-85079 *e 51-85026 *f [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 46 of 61 figure 22. 44-pin tqfp figure 23. 48-pin (7 7 mm) qfn 51-85064 *e pad exposed solderable 001-12919 *c [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 47 of 61 figure 24. 48-pin (300-mil) ssop figure 25. 48-pin qfn 7 7 0.90 mm (sawn type) 0.095 0.025 0.008 seating plane 0.420 0.088 .020 0.292 0.299 0.395 0.092 bsc 0.110 0.016 0.620 0.008 0.0135 0.630 dimensions in inches min. max. 0.040 0.024 0-8 gauge plane .010 1 24 25 48 0.004 0.005 0.010 51-85061 *d 001-13191 *e [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 48 of 61 figure 26. 100-pin tqfp important note for information on the preferred dimensions for mounting the qfn packages, see the application note application notes for surface mount assembly of amkor's microleadframe (mlf) packages available at http://www.amkor.com . important note pinned vias for thermal conduction are not required for the low-power psoc device. 51-85048 *e [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 49 of 61 thermal impedances capacitance on crystal pins solder reflow specifications ta b l e 4 1 shows the solder reflow temperature limits that must not be exceeded. table 39. thermal impedances per package package typical ja [ 23] 28-pin pdip 69 c/w 28-pin ssop 94 c/w 28-pin soic 67 c/w 44-pin tqfp 60 c/w 48-pin ssop 69 c/w 48-pin qfn [24] 28 c/w 100-pin tqfp 50 c/w notes 23. t j = t a + power ja. 24. to achieve the thermal impedance specified for the qfn package, refer to the applic ation notes for surface mount assembly of amkor's microleadframe (mlf) packages available at http://www.amkor.com . table 40. typical package capacitance on crystal pins package package capacitance 28-pin pdip 3.5 pf 28-pin ssop 2.8 pf 28-pin soic 2.7 pf 44-pin tqfp 2.6 pf 48-pin ssop 3.3 pf 48-pin qfn 1.8 pf 100-pin tqfp 3.1 pf table 41. solder reflow specifications package maximum peak temperature (t c ) maximum time above t c ? 5 c 28-pin pdip 260 c 30 seconds 28-pin ssop 260 c 30 seconds 28-pin soic 260 c 30 seconds 44-pin tqfp 260 c 30 seconds 48-pin ssop 260 c 30 seconds 48-pin qfn 260 c 30 seconds 100-pin tqfp 260 c 30 seconds [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 50 of 61 development tool selection this section presents the development tools available for all current psoc device families including the cy8c29x66 family. software psoc designer ? at the core of the psoc development software suite is psoc designer, used to generate psoc firmware applications. psoc designer is available free of charge at http://www.cypress.com and includes a free c compiler. psoc programmer flexible enough to be used on the bench in development, yet suitable for factory programming, psoc programmer works either as a standalone programming application or it can operate directly from psoc designer or psoc express. psoc programmer software is compatible with both psoc ice-cube in-circuit emulator and psoc miniprog. psoc programmer is available free of charge at http://www.cypress.com. development kits all development kits can be purchased from the cypress online store. cy3215-dk basic development kit the cy3215-dk is for prototyping and development with psoc designer. this kit supports in-circuit emulation and the software interface allows users to run, halt, and single step the processor and view the content of specific memory locations. advance emulation features also supported through psoc designer. the kit includes: psoc designer software cd ice-cube in-circuit emulator ice flex-pod for cy8c29x66 family cat-5 adapter mini-eval programming board 110 ~ 240 v power supply, euro-plug adapter imagecraft c compiler issp cable usb 2.0 cable and blue cat-5 cable two CY8C29466-24pxi 28-pdip chip samples evaluation tools all evaluation tools can be purchased from the cypress online store. cy3210-miniprog1 the cy3210-miniprog1 kit allows a user to program psoc devices via the miniprog1 programming unit. the miniprog is a small, compact prototyping programmer that connects to the pc via a provided usb 2.0 cable. the kit includes: miniprog programming unit minieval socket programming and evaluation board 28-pin CY8C29466-24pxi pdip psoc device sample 28-pin cy8c27443-24pxi pdip psoc device sample psoc designer software cd getting started guide usb 2.0 cable cy3210-psoceval1 the cy3210-psoceval1 kit features an evaluation board and the miniprog1 programming unit. the evaluation board includes an lcd module, potentiometer, leds, and plenty of bread- boarding space to meet all of your evaluation needs. the kit includes: evaluation board with lcd module miniprog programming unit 28-pin CY8C29466-24pxi pdip psoc device sample (2) psoc designer software cd getting started guide usb 2.0 cable cy3214-psocevalusb the cy3214-psocevalusb evaluation kit features a development board for the cy8c24794-24lfxi psoc device. special features of the board include both usb and capacitive sensing development and debugging support. this evaluation board also includes an lcd module, potentiometer, leds, an enunciator and plenty of bread boarding space to meet all of your evaluation needs. the kit includes: psocevalusb board lcd module miniprog programming unit mini usb cable psoc designer and example projects cd getting started guide wire pack [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 51 of 61 device programmers all device programmers can be purchased from the cypress online store. cy3216 modular programmer the cy3216 modular programmer kit features a modular programmer and the miniprog1 programming unit. the modular programmer includes three programming module cards and supports multiple cypress products. the kit includes: modular programmer base three programming module cards miniprog programming unit psoc designer software cd getting started guide usb 2.0 cable cy3207issp in-system serial programmer (issp) the cy3207issp is a production programmer. it includes protection circuitry and an industrial case that is more robust than the miniprog in a production-programming environment. note cy3207issp needs special software and is not compatible with psoc programmer. the kit includes: cy3207 programmer unit psoc issp software cd 110 ~ 240 v power supply, euro-plug adapter usb 2.0 cable accessories (emulation and programming) table 42. emulation and programming accessories part # pin package flex-pod kit [25] foot kit [26] adapter [27] CY8C29466-24pxi 28-pin pdip cy 3250-29xxx cy3250-28pdip-fk adapters can be found at http://www.emulation.com. CY8C29466-24pvxi 28-pin ssop cy 3250-29xxx cy3250-28ssop-fk CY8C29466-24sxi 28-pin soic cy 3250-29xxx cy3250-28soic-fk cy8c29566-24axi 44-pin tqfp cy 3250-29xxx cy3250-44tqfp-fk cy8c29666-24pvxi 48-pin ssop cy 3250-29xxx cy3250-48ssop-fk cy8c29666-24ltxi 48-pin qfn c y3250-29xxxqfn cy3250-48qfn-fk cy8c29866-24axi 100-pin tqfp cy 3250-29xxx cy3250-100tqfp-fk notes 25. flex-pod kit includes a practice flex-pod and a practice pcb, in addition to two flex-pods. 26. foot kit includes surface mount feet th at can be soldered to the target pcb. 27. programming adapter converts non-dip pack age to dip footprint. specific details a nd ordering information for each of the ada pters can be found at http://www.emulation.com [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 52 of 61 ordering information the following table lists the cy8c29x66 psoc device?s key package features and ordering codes. note for die sales information, contact a local cypre ss sales office or field applications engineer (fae). ordering code definitions package ordering code flash (kb) ram (kb) switch mode pump temperature range digital psoc blocks analog psoc blocks digital i/o pins analog inputs analog outputs xres pin 28-pin (300-mil) dip CY8C29466-24pxi 32 2 yes ?40 c to +85 c 16 12 24 12 4 yes 28-pin (210-mil) ssop CY8C29466-24pvxi 32 2 yes ?40 c to +85 c 16 12 24 12 4 yes 28-pin (210-mil) ssop (tape and reel) CY8C29466-24pvxit 32 2 yes ?40 c to +85 c 16 12 24 12 4 yes 28-pin (300-mil) soic CY8C29466-24sxi 32 2 yes ?40 c to +85 c 16 12 24 12 4 yes 28-pin (300-mil) soic (tape and reel) CY8C29466-24sxit 32 2 yes ?40 c to +85 c 16 12 24 12 4 yes 44-pin tqfp cy8c29566-24axi 32 2 yes ?40 c to +85 c 16 12 40 12 4 yes 44-pin tqfp (tape and reel) cy8c29566-24axit 32 2 yes ?40 c to +85 c 16 12 40 12 4 yes 48-pin (300-mil) ssop cy8c29666-24pvxi 32 2 yes ?40 c to +85 c 16 12 44 12 4 yes 48-pin (300-mil) ssop (tape and reel) cy8c29666-24pvxit 32 2 yes ?40 c to +85 c 16 12 44 12 4 yes 100-pin tqfp cy8c29866-24axi 32 2 yes ?40 c to +85 c 16 12 64 12 4 yes 100-pin ocd tqfp [28] cy8c29000-24axi 32 2 yes ?40 c to +85 c 16 12 64 12 4 yes 48-pin (7 7 1.0 mm) qfn (sawn) cy8c29666-24ltxi 32 2 yes ?40 c to +85 c 16 12 44 12 4 yes 48-pin (7 7 1.0 mm) qfn (sawn) cy8c29666-24ltxit 32 2 yes ?40 c to +85 c 16 12 44 12 4 yes note 28. this part may be used for in-circuit debugging. it is not available for production. cy 8 c 29 xxx-spxx package type: thermal rating: px = pdip pb-free c = commercial sx = soic pb-free i = industrial pvx = ssop pb-free e = extended lfx/lkx/ltx/lqx/lcx = qfn pb-free ax = tqfp pb-free speed: 24 mhz part number family code technology code: c = cmos marketing code: 8 = cypress psoc company id: cy = cypress [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 53 of 61 acronyms acronyms used ta b l e 4 3 lists the acronyms that are used in this document. reference documents cy8cplc20, cy8cled16p01, cy8c29x66, cy8c27x43, cy8c24 x94, cy8c24x23, cy8c24x23a, cy8c22x13, cy8c21x34, cy8c21x23, cy7c64215, cy7c603xx, cy8cnp1xx, and cywusb6953 psoc ? programmable system-on-chip technical reference manual (trm) (001-14463) design aids ? reading and writing psoc ? flash - an2015 (001-40459) adjusting psoc ? trims for 3.3 v and 2.7 v operation ? an2012 (001-17397) understanding datasheet jitter specifications for cypress timing products ? an5054 (001-14503) application notes for surface mount assembly of amkor's microleadframe (mlf) packages ? available at http://www.amkor.com . table 43. acronyms used in this datasheet acronym description acronym description ac alternating current mips million instructions per second adc analog-to-digital converter ocd on-chip debug api application programming interface pcb printed circuit board cmos complementary metal oxide semiconductor pdip plastic dual-in-line package cpu central processing unit pga programmable gain amplifier crc cyclic redundancy check pll phase-locked loop ct continuous time por power on reset dac digital-to-analog converter ppor precision power on reset dc direct current prs pseudo-random sequence dtmf dual-tone multi-frequency psoc ? programmable system-on-chip eco external crystal oscillator pwm pulse width modulator eeprom electrically erasable programmable read-only memory qfn quad flat no leads gpio general purpose i/o rtc real time clock ice in-circuit emulator sar successive approximation ide integrated development environment sc switched capacitor ilo internal low speed oscillator smp switch mode pump imo internal main oscillator soic small-outline integrated circuit i/o input/output spi serial peripheral interface irda infrared data association sram static random access memory issp in-system serial programming srom supervisory read only memory lcd liquid crystal display ssop shrink small-outline package led light-emitting diode tqfp thin quad flat pack lpc low power comparator uart universal asynchronous reciever / trans- mitter lvd low voltage detect usb universal serial bus mac multiply-accumulate wdt watchdog timer mcu microcontroller unit xres external reset [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 54 of 61 document conventions units of measure ta b l e 4 4 lists the unit sof measures. numeric conventions hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? pref ix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). nu mbers not indicated by an ?h?, ?b?, or 0x are decimals. table 44. units of measure symbol unit of measure symbol unit of measure db decibels ms millisecond c degree celsius ns nanosecond ff femto farad ps picosecond pf picofarad v microvolts khz kilohertz mv millivolts mhz megahertz mvpp millivolts peak-to-peak rt-hz root hertz nv nanovolts k kilohm v volts ohm w microwatts a microampere w watt ma milliampere mm millimeter na nanoampere ppm parts per million pa pikoampere % percent s microsecond glossary active high 1. a logic signal having its asserted state as the logic 1 state. 2. a logic signal having the logic 1 state as the higher voltage of the two states. analog blocks the basic programmable opamp circuits. these are sc (switched capacitor) and ct (continuous time) blocks. these blocks can be interconnected to provide adcs, dacs, mu lti-pole filters, gain stages, and much more. analog-to-digital (adc) a device that changes an analog signal to a digital signal of corresponding magnitude. typically, an adc converts a voltage to a digital number. the digital-to-analog (dac) converter performs the reverse operation. application programming interface (api) a series of software routines that comprise an interface between a computer application and lower level services and functions (for example, user modules and libraries). apis serve as building blocks for progr ammers that create software applications. asynchronous a signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. bandgap reference a stable voltage reference design that matches the positive temperature coefficient of vt with the negative temperat ure coefficient of vbe, to produce a ze ro temperature coefficient (ideally) reference. bandwidth 1. the frequency range of a message or information processing system measured in hertz. 2. the width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as, for example, full width at half maximum. [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 55 of 61 bias 1. a systematic deviation of a value from a reference value. 2. the amount by which the average of a set of values departs from a reference value. 3. the electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. block 1. a functional unit that performs a single function, such as an oscillator. 2. a functional unit that may be configured to perform one of several functions, such as a digital psoc block or an analog psoc block. buffer 1. a storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. usually refers to an area reserved for io operations, into which data is read, or from which data is written. 2. a portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. an amplifier used to lower the output impedance of a system. bus 1. a named connection of nets. bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. a set of signals performing a common function and carrying similar data. typically represented using vector notation; for example, address[7:0]. 3. one or more conductors that serve as a common connection for a group of related devices. clock the device that generates a periodic signal with a fixed fr equency and duty cycle. a clock is sometimes used to synchroni ze different logic blocks. comparator an electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. compiler a program that translates a high level language, such as c, into machine language. configuration space in psoc devices, the register space accessed when the xio bit, in the cpu_f register, is set to ?1?. crystal oscillator an oscillator in which the frequency is controlled by a piezoelectric crystal. typically a piezoelectric crystal is less sensitive to ambient temperature than other circuit components. cyclic redundancy check (crc) a calculation used to detect errors in data communications, typically performed using a linear feedback shift register. similar calculations may be used for a variety of other purposes such as data compression. data bus a bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. more generally, a set of signals used to convey data between digital functions. debugger a hardware and software system that allo ws you to analyze the operation of the system under development. a debugger usually allows th e developer to step through the firmware one step at a time, set break points, and analyze memory. dead band a period of time when neither of two or more signals are in their active state or in transition. digital blocks the 8-bit logic blocks that can act as a counter, timer, se rial receiver, serial transmitter, crc generator, pseudo-random number generator, or spi. glossary (continued) [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 56 of 61 digital-to-analog (dac) a device that changes a digital signal to an analog signal of corresponding magnitude. the analog- to-digital (adc) converter performs the reverse operation. duty cycle the relations hip of a clock period high time to its low time, expressed as a percent. emulator duplicates (provides an emul ation of) the functions of one system with a different system, so that the second system appears to behave like the first system. external reset (xres) an active high signal that is driven into the psoc device. it causes all operation of the cpu and blocks to stop and return to a pre-defined state. flash an electrically programmable and erasable, non-volatile technology that provides you the programmability and data storage of eproms, pl us in-system erasability. non-volatile means that the data is retained when power is off. flash block the smallest amount of flash rom space that may be programmed at one time and the smallest amount of flash space that may be protected. a flash block holds 64 bytes. frequency the number of cycles or events pe r unit of time, for a periodic function. gain the ratio of output current, voltage, or power to input current, voltage, or power, respectively. gain is usually expressed in db. i 2 c a two-wire serial computer bus by philips semiconductors (now nxp semiconductors). i2c is an inter-integrated circuit. it is used to connec t low-speed peripherals in an embedded system. the original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control el ectronics. i2c uses only two bi-d irectional pins, clock and data, both running at +5v and pulled high with resistors. the bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode. ice the in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging device activity in a software environment (psoc designer). input/output (i/o) a device that introduces data into or extracts data from a system. interrupt a suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service routine (isr) a block of code that normal code execution is diverted to when the m8c receives a hardware interrupt. many interrupt sources may each exist with its own priority and individual isr code block. each isr code block ends with the reti instruction, returning the device to the point in the program where it left normal program execution. jitter 1. a misplacement of the timing of a transition from its ideal position. a typical form of corruption that occurs on serial data streams. 2. the abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequen cy or phase of successive cycles. low-voltage detect (lvd) a circuit that senses v dd and provides an interrupt to the system when v dd falls lower than a selected threshold. m8c an 8-bit harvard-architecture microprocessor. the microprocessor coordinates all activity inside a psoc by interfacing to the flash, sram, and register space. glossary (continued) [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 57 of 61 master device a device that controls the timing for data exchanges between two devices. or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. the controlled device is called the slave device . microcontroller an integrated circuit chip that is desi gned primarily for control systems and products. in addition to a cpu, a microcontroller typically includes memory, timing circuits, and io circuitry. the reason for this is to permit the realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. this in turn, reduces the volume and the cost of the controller. the microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal the reference to a circuit containing both analog and digital techniques and components. modulator a device that imposes a signal on a carrier. noise 1. a disturbance that affects a signal and that may distort the information carried by the signal. 2. the random variations of one or more characteristi cs of any entity such as voltage, current, or data. oscillator a circuit that may be crystal controlled and is used to generate a clock frequency. parity a technique for testing transmitting data. typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). phase-locked loop (pll) an electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. pinouts the pin number assignment: the relation between the logical inputs and outputs of the psoc device and their physical counterparts in the printed circuit board (pcb) package. pinouts involve pin numbers as a link between schematic and pcb design (both being computer generated files) and may also involve pin names. port a group of pins, usually eight. power on reset (por) a circuit that forces the psoc device to reset when the voltage is lower than a pre-set level. this is a type of hardware reset. psoc ? cypress semiconductor?s psoc ? is a registered trademark and programmable system-on- chip? is a trademark of cypress. psoc designer? the software for cypress? programmable system-on-chip technology. pulse width modulator (pwm) an output in the form of duty cycle which varies as a function of the applied measurand ram an acronym for random access memory. a data-storage device from which data can be read out and new data can be written in. register a storage device with a specific capacity, such as a bit or byte. reset a means of bringing a system back to a know state. see hardware reset and software reset. rom an acronym for read only memory. a data-storage device from which data can be read out, but new data cannot be written in. glossary (continued) [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 58 of 61 serial 1. pertaining to a process in which all events occur one after the other. 2. pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. settling time the time it takes for an output signal or value to stabilize after the input has changed from one value to another. shift register a memory storage device that sequentially shif ts a word either left or right to output a stream of serial data. slave device a device that allows another device to control the timing for data exchanges between two devices. or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. the controlling device is called the master device. sram an acronym for static random access memory. a memory device where you can store and retrieve data at a high rate of speed. the term static is used because, after a value is loaded into an sram cell, it remains unchanged until it is explicitly al tered or until power is removed from the device. srom an acronym for supervisory read only memory . the srom holds code that is used to boot the device, calibrate circuitry, and perform flash operations. the functions of the srom may be accessed in normal user code, operating from flash. stop bit a signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1. a signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. a system whose operation is synchronized by a clock signal. tri-state a function whose output can adopt three stat es: 0, 1, and z (high-impedance). the function does not drive any value in the z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowing another output to drive the same net. uart a uart or universal asynchronous receiver-tra nsmitter translates between parallel bits of data and serial bits. user modules pre-build, pre-tested hardw are/firmware peripheral functions that take care of managing and configuring the lower level analog and digital psoc blocks. user modules also provide high level api (application programming interface) for the peripheral function. user space the bank 0 space of the register map. the re gisters in this bank are more likely to be modified during normal program execution and not just durin g initialization. registers in bank 1 are most likely to be modified only during the initialization phase of the program. v dd a name for a power net meaning "voltage drain." the most positive power supply signal. usually 5 v or 3.3 v. v ss a name for a power net meaning "voltage source." the most negative power supply signal. watchdog timer a timer that must be serviced periodically. if it is not serviced, the cpu resets after a specified period of time. glossary (continued) [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 59 of 61 document history page document title: CY8C29466, cy8c 29566, cy8c29666, cy8c29866 psoc ? programmable system-on-chip? document number: 38-12013 revision ecn origin of change submis- sion date description of change ** 131151 new silicon 11/13/2003 new document (revision **). *a 132848 nwj 01/21/2004 new information. first edition of preliminary datasheet. *b 133205 nwj 01/27/2004 changed part numbers, increased sram data storage to 2 k bytes. *c 133656 sfv 02/09/2004 changed part numbers and removed a 28-pin soic. *d 227240 sfv 06/01/2004 changes to overview section, 48-pin mlf pinout, and significant changes to the electrical specs. *e 240108 sfv see ecn added a 28-lead (300 mil) soic part. *f 247492 sfv see ecn new information added to the electrical specifications chapter. *g 288849 hmt see ecn add ds standards, update device table, fine-tune pinouts, add reflow peak temp. table. finalize. *h 722736 hmt see ecn add qfn package clarifications. add new qfn diagram. add low power comparator (lpc) ac/dc electrical sp ec. tables. add cy8c20x34 to psoc device characteristics table. update emulation pod/feet kit part numbers. add ocd non-production pinouts and package diagrams. add issp note to pinout tables. update package diagram revisions. update typical and recommended storage temperature per industrial specs. update cy branding and qfn convention. add new dev. tool section. update copyright and trademarks. *i 2503350 dfk/pyrs see ecn pinout for cy8c29000 ocd wrongly included details of cy8c24x94. the correct pinout for cy8c29000 is included in this version. added note on digital signaling in ?dc analog reference specifications? section. *j 2545030 yara 07/29/08 added note to ordering information *k 2708295 jvy 04/22/2009 changed title from ?CY8C29466, cy8c29566, cy8c29666, and cy8c29866 psoc mixed signal array final datasheet? to ?CY8C29466, cy8c29566, cy8c29666, and cy8c29866 psoc ? programmable system-on-chip?? updated to datasheet template added 48-pin qfn (sawn) package diagram and cy8c29666-24ltxi and cy8c29666-24ltxit part details in the ordering information table updated dc gpio, ac chip-level, and ac programming specifications as follows: modified f imo6 (page 27), t write specifications (page 34) added i oh (page 21), i ol (page 21), dc ilo (page 28), f 32k_u (page 27), t powerup (page 28), t eraseall (page 34), t program_hot (page 34), and t program_cold (page 34) specifications *l 2761941 drsw/aesa 09/10/2009 added sr power_up parameter in ac specs table . . *m 2842762 drsw 01/08/2010 corrected notes for v dd parameter in table 13, ?dc chip-level specifica- tions,? on page 20. added ?contents? on page 2. updated links in sales, solutions, and legal information . [+] feedback
CY8C29466, cy8c29566 cy8c29666, cy8c29866 document number: 38-12013 rev. *s page 60 of 61 *n 2902396 njf 03/30/2010 updated digital system block diagram and content in digital system updated cypress website links. removed reference to psoc designer 4.4 in psoc designer software subsystems added t baketemp and t baketime parameters in absolute maximum ratings updated ac chip-level specifications changed unit for spis function to ns in ac digital block specifications updated notes in packaging information and package diagrams. updated solder reflow specifications updated emulation and programming accessories removed third party tools and build a psoc emulator into your board. updated ordering information and ordering code definitions . *o 2940410 yji 05/31/2010 updated content to match current style guide and datasheet template. no technical updates. *p 3044869 njf 10/01/2010 added psoc device characteristics table . added dc i 2 c specifications table. added f 32k_u max limit. added tjit_imo specification, remo ved existing jitter specifications. updated analog reference tables. updated units of measure, acronyms, glossary, and references sections. updated solder reflow specifications. no specific changes were made to ac digital block specifications table and i 2 c timing diagram. they were updated for clearer understanding. updated figure 13 since the labelling for y-axis was incorrect. template and styles update. removed footnote reference for ?solde r reflow peak temperature? table. *q 3017427 gdk 11/08/10 removed the pruned part ?cy8c29666-24lfxi? from the ordering information and accessories (emulation and programming) . *r 3263978 njf 05/23/11 updated logic block diagram . updated solder reflow specifications . *s 3301676 njf 07/04/11 fixed page numbering error on footer. document title: CY8C29466, cy8c 29566, cy8c29666, cy8c29866 psoc ? programmable system-on-chip? document number: 38-12013 revision ecn origin of change submis- sion date description of change [+] feedback
document number: 38-12013 rev. *s revised july 7, 2011 page 61 of 61 psoc designer? and programmable system-on-chip? are trademarks and psoc? and capsense? are registered trademarks of cypress sem iconductor corporation. purchase of i 2 c components from cypress or one of its sublicensed associat ed companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. as from october 1st, 2006 philips semiconductors has a new trade name - nxp sem iconductors. all products and company names mentioned in this document may be the trademarks of their respective holders. CY8C29466, cy8c29566 cy8c29666, cy8c29866 ? cypress semiconductor corporation, 2003-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypre ss.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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